RETRACTED ARTICLE: Model for estimating power dissipation along the interconnect length in single on-chip topology

Designing a typical microcircuit for multi-core chips includes the development of the overall system architecture as well as the creation of single-chip multiprocessor systems, which house a set of interrelated nodes. To evaluate the complexity and power consumption of these multiprocessor systems, adequate models and methods are required. A simplified model for calculating heat dissipation in conductors suits this purpose completely. The preliminary settlement of the heat dissipation parameter will allow engineers to evaluate the on-chip interconnect topology at the early stages of design so that these interconnects comply with the power dissipation and the power consumption variables. The novelty of this approach lies in the fact that it allows modeling thermal stresses that take place inside the chip. A solver applied here enables numerical solution to differential equations that is theoretically best, i.e., a direct numerical solution. In addition, it overcame the Gibbs phenomenon by incorporating more natural, not sharp boundary conditions into the model. Here, this approach was applied to the multiprocessor system design that implies the integration of processor cores in a single chip package.