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Published in:
2013 | OriginalPaper | Chapter
12. Multi Cycle Paths
Authors : Sridhar Gangadharan, Sanjay Churiwala
Published in: Constraining Designs for Synthesis and Timing Analysis
Publisher: Springer New York
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Abstract
By default, each path is timed for a single cycle, i.e., data launched at any edge of the clock should be captured by the next flop at the next rising edge of the clock on the destination flop. Figure 12.1 shows this relationship.