Top

Published in:

2010 | OriginalPaper | Chapter

2. NAND overview: from memory to systems

Authors : R. Micheloni, A. Marelli, S. Commodaro

Published in: Inside NAND Flash Memories

Publisher: Springer Netherlands

Activate our intelligent search to find suitable subject content or patents.

search-config

AI-assisted search

Off

Abstract

It was in 1965, just after the invention of the bipolar transistor by W. Shockley, W. Brattain and J. Bardeen, that Gordon Moore, co-founder of Intel, observed that the number of transistors per square centimeter in a microchip doubled every year. Moore thought that such trend would have proven true for the years to come as well, and indeed in the following years the density of active components in an integrated circuit kept on doubling every 18 months. For example, in the 18 months that elapsed between the Pentium processor 1.3 and the Pentium-4, the number of transistors grew from 28 to 55 million.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

inform now

previous chapter Market and applications for NAND Flash memories

next chapter Program and erase of NAND memory arrays

G. Campardo, R. Micheloni, D. Novosel, “VLSI-Design of Non-Volatile Memories”, Springer-Verlag, 2005.

R. H. Fowler and L. Nordheim, “Electron Emission in Intense Electric Fields,” Proceedings of the Royal Society of London, Vol. 119, No. 781, May 1928, pp. 173–181.

www.mmca.org

www.compactFlash.org

www.sdcard.com

A. Kawaguchi, S. Nishioka, and H. Motoda. “A Flash-Memory Based File System”, Proceedings of the USENIX Winter Technical Conference, pp. 155–164, 1995.

J. Kim, J. M. Kim, S. Noh, S. L. Min, and Y. Cho. “A Space-Efficient Flash Translation Layer for CompactFlash Systems,” IEEE Transactions on Consumer Electronics, Vol. 48, No. 2, May 2002, pp.366–375.

S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S.-W. Park, and H.-J. Songe. “FAST: A Log-Buffer Based FTL Scheme with Fully Associative Sector Translation”, 2005 US-Korea Conference on Science, Technology, and Entrepreneurship, August 2005.

T. Tanzawa, T. Tanaka, K. Takekuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takekuchi, and K. Ohuchi, “A Compact On-Chip ECC for Low Cost Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 32, May 1997, pp. 662–669.CrossRef

10.

G. Campardo, R. Micheloni et al.,“40-mm² 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR Flash memory,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, Nov. 2000, pp. 1655–1667.

11.

R. Micheloni et al., “A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput”, IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 142–143, Feb. 2006.

12.

R. Micheloni, A. Marelli, R. Ravasio, “Error Correction Codes for Non-Volatile Memories”, Springer-Verlag, 2008.

13.

C. Park et al., “A High Performance Controller for NAND Flash-based Solid State Disk (NSSD)”, IEEE Non-Volatile Semiconductor Memory Workshop NVSMW, pp. 17–20, Feb. 2006.

14.

D. Nobunaga et al., “A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface”, IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 426–427, Feb. 2008.

15.

K. Kanda et al., “A 120mm² 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology”, in IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 430–431, Feb. 2008.

16.

Chang Gyu Hwang, “New Paradigms in the Silicon Industry, International Electron Device Meeting (IEDM), 2006, pp. 1–8.

17.

M. Kawano et al., “A 3D Packaging Technology for a 4Gbit Stacked DRAM with 3Gbps Data Transfer, International Electron Device Meeting (IEDM), 2006, pp. 1–4.

18.

M. Motoyoshi, “Through-Silicon Via (TSV)”, Proceedings of the IEEE, Vol. 97, Jan. 2009, pp. 43–48.

19.

M. Koyanagi et al., “High-Density Through Silicon Vias for 3-D LSIs”, Proceedings of the IEEE, Vol. 97, Jan. 2009, pp. 49–59.

20.

G. Campardo, M. Iaculo, F. Tiziani (Eds.), “Memory Mass Storage”, Chap. 6, Springer, 2010.

21.

S.-M. Jung, J. Jang, W. Cho et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node,” IEDM Dig. Tech. Papers, pp. 37–40, Dec. 2006.

22.

K. T. Park et al.,” A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure”, IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 510–511, Feb. 2008.

23.

H. Tanaka, M. Kido, K. Yahashi et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Flash Memory,” Dig. Symp. VLSI Technology, pp. 14–15, June 2006.

24.

R. Katsumata et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices”, 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 136–137.

Title: NAND overview: from memory to systems
Authors: R. Micheloni
A. Marelli
S. Commodaro
Publisher: Springer Netherlands
Book: Inside NAND Flash Memories
Print ISBN: 978-90-481-9430-8

Electronic ISBN: 978-90-481-9431-5

Copyright Year: 2010
DOI: https://doi.org/10.1007/978-90-481-9431-5_2