Noise-Shaping All-Digital Phase-Locked Loops

An All Digital Phase Locked Loop (ADPLL) is an alternative to a traditional Phase Locked Loop (PLL) for implementation in nanoscale digital CMOS, especially as part of a system-on-chip (SoC) [1, 2]. One of the key advantages of ADPLLs over their analog counterparts is that they remove the need for large capacitors within the loop filter by utilizing digital circuits to achieve the desired filtering function.

In this chapter, we review the operating principles of the main topologies of ADPLLs (PFD-plus-TDC-based, TDC-based and accumulator-based ADPLLs) in terms of the integer and fractional parts of the phase difference. We also mention the flip-flop-based ADPLL which can be considered as a particular case of a TDC-based ADPLL. We show models that describe the phase-to-digital conversion in each ADPLL architecture when the integer part of the phase difference is equal to or different from zero. We show that a flip-flop based ADPLL can be viewed as the ADPLL architecture with the simplest phase-to-digital conversion. We also discuss possible strategies to clock the digital filter in the various ADPLL architectures. We show how to modify the ADPLL architectures to synthesize a fractional ratio between the frequencies of the reference oscillator and the DCO. Finally, we compare the ADPLL architectures in terms of phase-to-digital conversion, TDC dynamic range, and metastability.

A TDC is an analog-to-digital converter that converts the duration of a time interval to a digital word [1].

In this chapter, we will derive analytical predictions of the phase noise in TDC-based and accumulator-based ADPLLs with \(l\)th-order noise shaping TDCs and DCO driven by a sigma-delta modulator.

We have shown in Chap. 3 that zeroth and first-order noise-shaping TDCs can be modelled by quantizers and first-order sigma-delta modulators, respectively. In this chapter, we consider the cases in which a dither signal \({\textit{dtr}}[n]\) is added to the input \(in[n]\) of a quantizer or a sigma-delta modulator followed by a moving average filter. In order to keep our analysis simple, we assume that \(\textit{dtr}[n]\) is uniformly distributed over the interval \([-\varDelta d/2, \varDelta d/2]\). Dither has the effect of making the quantization errors that are associated with the quantizer and the sigma-delta modulator more white and uniformly distributed over their intervals of definition. The moving average filters remove part of the noise associated with the dither and the quantization error. The removal of part of the power of the quantization error corresponds to an increase in the effective precision of a quantizer or a sigma-delta modulator when followed by a moving average filter. We determine analytically the precisions of these systems in terms of the maximum difference between the input and the output when this difference is bounded. In the cases where the maximum difference between the input and output is unbounded (because its distribution is Gaussian, for example), we assume that a measure of the precision of a quantizer or a sigma–delta modulator is the size of the interval \([-3\sigma , 3\sigma ]\) of the contributions of the quantization error and the dither to the output, where \(\sigma \) is the standard deviation.

In this chapter, we focus on the behavioral modeling and simulation of accumulator-based ADPLLs. First, we introduce some basic concepts related to mixed-signal systems and simulators. We highlight the major issues for the simulation of an ADPLL as an example mixed-signal system.

The goal of this chapter is to illustrate how to model and estimate the phase noise of a sampled signal using Matlab. We first illustrate how the phase noise of a signal is related to the phase deviations of the signal. We then show how to model the phase noise of a noisy signal using Matlab.