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Published in:
2007 | OriginalPaper | Chapter
Parallel Matrix Multiplication Based on Dynamic SMP Clusters in SoC Technology
Authors : Marek Tudruj, Łukasz Masko
Published in: Frontiers of High Performance Computing and Networking ISPA 2007 Workshops
Publisher: Springer Berlin Heidelberg
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The paper concerns a special architecture of dynamic shared memory processor (SMP) clusters organized at program run-time. In this architecture, designed for implementation in System on Chip technology, a new mechanism of the communication on the fly is provided. It is a combination of dynamic processor switching between SMP clusters and parallel data reads on the fly. This mechanism enables direct communication between processor data caches and eliminates many data transactions on memory busses. The paper presents the principles of the new architecture and evaluates its efficiency for execution of matrix multiplication with recursive matrix decomposition into quarters. The evaluation is done by simulation experiments with symbolic execution of parallel program graphs with different parallelization grain.