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A Throughput Enhanced JTIDS Waveform Design Read chapter Read first chapter

2018 | OriginalPaper | Chapter

Parallel Symbol Timing Recovery Using FPGA for 600 Msps QPSK

Authors : Di Huang, Zhijie Wang, Jun Wang, ZiYao Liu

Published in: Communications and Networking

Publisher: Springer International Publishing

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Abstract

This paper presents an efficient parallel symbol timing architecture for high data rate communications receivers. The presented architecture relies on a modified version of the classic Gardner loop, and it features a “multi-channel pipeline” interpolator that enables the symbol rate to be several times higher than the clock rate of the FPGA, hence maximize the achievable throughput. The presented timing recovery scheme is demonstrated on a Xilinx XC7VX690T FPGA at 150 MHz clock rate together with an ADC at 4.8 GHz sampling rate, for an QPSK data-stream at 600 Msps symbol rate. Also, it is observed the presented scheme occupies only 2% of the logic, storage and computational resources in the targeted FPGA. With minor modifications, our algorithm may be adapted for other Amplitude-Phase modulation constellations such as 8PSK, 16PSK or QAM.

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Metadata
Title
Parallel Symbol Timing Recovery Using FPGA for 600 Msps QPSK
Authors
Di Huang
Zhijie Wang
Jun Wang
ZiYao Liu
Copyright Year
2018
Publisher
Springer International Publishing
Book
Communications and Networking

Print ISBN: 978-3-319-78129-7

Electronic ISBN: 978-3-319-78130-3

Copyright Year: 2018

DOI
https://doi.org/10.1007/978-3-319-78130-3_23

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