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Published in:
2011 | OriginalPaper | Chapter
Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization
Authors : Avinash Lingamneni, Christian Enz, Krishna Palem, Christian Piguet
Published in: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
Publisher: Springer Berlin Heidelberg
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Contrary to the existing techniques to realize
inexact
circuits that relied mostly on scaling of supply voltage or pruning of “least-significant” components in conventional correct circuits to achieve cost (energy, delay and/or area) and accuracy tradeoffs, we propose a novel technique called
Probabilistic Logic Minimization
which relies on synthesizing an inexact circuit in the first place resulting in
zero hardware overhead
. Extensive simulations of the datapath elements designed using the proposed technique demonstrate that normalized gains as high as 2X-9.5X in the Energy-Delay-Area product can be obtained when compared to the corresponding correct designs, with a relative error magnitude percentage as low as 0.001% upto 1%.