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Published in:
2011 | OriginalPaper | Chapter
Performance-Driven Clustering of Asynchronous Circuits
Authors : Georgios D. Dimou, Peter A. Beerel, Andrew M. Lines
Published in: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
Publisher: Springer Berlin Heidelberg
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This paper describes a novel approach for generating asynchronous circuits from HDL specifications by clustering the synthesized gates into asynchronous pipeline stages while preserving liveness, meeting throughput constraints, and minimizing area. The method enables a form of automatic re-pipelining in which the throughput of the resulting design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The method is design-style agnostic and is thus applicable to many asynchronous design styles.