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Published in:
2013 | OriginalPaper | Chapter
9. Port Delays
Authors : Sridhar Gangadharan, Sanjay Churiwala
Published in: Constraining Designs for Synthesis and Timing Analysis
Publisher: Springer New York
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Abstract
Once the clock constraints have been applied, all the register to register paths can be timed. Now, the delay constraints have to be applied on non-clock ports. If input and output port constraints are not specified, timing analysis tools assume a highly optimistic timing requirements on the interfaces. They assume the combinational logic inside the block can have the entire period to itself and leave nothing for the portion of the signal outside the block.