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2013 | OriginalPaper | Chapter

Power Consumption of Kernel Operations

Authors : Dmitry Khabi, Uwe Küster

Published in: Sustained Simulation Performance 2013

Publisher: Springer International Publishing

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Abstract

A modern Petascale System consists of millions of different components, which consume a huge amount of energy. The power rating of each component depends on the type of the current instructions, executed on cores, memory controllers, network units and other various components. There are a lot of influences and complicated dependencies between the software, environment and the energy consumption. The objective of this work is to identify and understand the energy consumption of processors and memory in the consideration of kernel operations. Another important goal is to develop the methodology by which the developers and users could estimate the energy consumption of the different algorithms on different systems with minimal effort and satisfying accuracy.

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Footnotes
1
We do not run any calculations on the weak graphics card and the fans run at a constant speed. We assume that the power consumption of these components is constant. This was also confirmed with a series of extra tests.
 
2
We vary the number of active cores, frequency and hierarchy levels of memory, on that the processor operates.
 
3
The best approximation for the same kernel operation Add on Sandy Bridge Intel i5-2500 (6 M Cache, up to 3.7 GHz, 4 cores) is by ρ = 2. 7.
 
4
If we compare the obtained values to the data from the article [6] we see that the energy consumption of Sandy Bridge (E5-2687W) and of the previous generation Westmere (Intel XEON X5670) are within the same order of magnitude.
 
Literature
3.
go back to reference S. Williams, A. Waterman and D. Patterson. Roofline: An Insightful Visual Performance Model for Multicore Architectures Communications of the ACM, Vol. 52, No. 4. (April 2009), pp. 65–76, doi:10.1145/1498765.1498785 S. Williams, A. Waterman and D. Patterson. Roofline: An Insightful Visual Performance Model for Multicore Architectures Communications of the ACM, Vol. 52, No. 4. (April 2009), pp. 65–76, doi:10.1145/1498765.1498785
4.
go back to reference Robert Chappell, Bret Toll, Ronal Singhal, Intel Next Generation Micro Architecture Codename Haswell: New Processor Innovations. Presented at IDF (2012) Robert Chappell, Bret Toll, Ronal Singhal, Intel Next Generation Micro Architecture Codename Haswell: New Processor Innovations. Presented at IDF (2012)
5.
go back to reference Markus Wittmann, Georg Hager, Thomas Zeiser, Gerhard Wellein. An analysis of energy-optimized lattice-Boltzmann CFD simulations from the chip to the highly parallel level arXiv:1304.7664 (April 2013) Markus Wittmann, Georg Hager, Thomas Zeiser, Gerhard Wellein. An analysis of energy-optimized lattice-Boltzmann CFD simulations from the chip to the highly parallel level arXiv:1304.7664 (April 2013)
6.
go back to reference Daniel Molka, Daniel Hackenberg, Robert Schöne and Matthias S. Müller, Characterizing the Energy Consumption of Data Transfers and Arithmetic Operations on x86-64 Processors, Proceeding of the first International Green Computing Conference, (August 2010) Daniel Molka, Daniel Hackenberg, Robert Schöne and Matthias S. Müller, Characterizing the Energy Consumption of Data Transfers and Arithmetic Operations on x86-64 Processors, Proceeding of the first International Green Computing Conference, (August 2010)
Metadata
Title
Power Consumption of Kernel Operations
Authors
Dmitry Khabi
Uwe Küster
Copyright Year
2013
DOI
https://doi.org/10.1007/978-3-319-01439-5_3

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