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Published in:
2019 | OriginalPaper | Chapter
8. Practical Implementation Issues
Author : Sung-Moon Michael Yang
Published in: Modern Digital Radio Communication Signals and Systems
Publisher: Springer International Publishing
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Abstracts
This chapter covers transceiver architectures – direct conversion, heterodyne conversion, and low digital IF image-cancelling transceiver – transmit RF signal generation, and receiver RF signal processing. We examine the required number of bits and the optimum power level for DAC and ADC. A particular emphasis is on low digital IF image-cancelling transceiver; it is described in great detail so that one skilled in the art of transceiver can implement. The quality measurement of quadrature modulator (demodulator) related with DC offset and quadrature imbalance is explained in detail so that they can be calibrated as well.
List of Sections
8.1.
Transceiver Architecture
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Transceiver of low digital IF with image cancelling
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Calibration of quadrature modulator/demodulator
8.2.
Practical Issues of RF Transmit Signal Generation
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DAC
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PA and non-linearity
8.3.
Practical Issues of RF Receive Signal Processing
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ADC
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RCV dynamic range and AGC
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VLNA, NF, and receiver sensitivity threshold
8.4.
Chapter Summary and References with Comments