Preliminary Performance and Programmability Comparison of the Thick Control Flow Architecture and Current Multicore CPUs

Multicore CPUs integrate a number of processor cores on a single chip to support parallel execution of computational tasks. These CPUs improve the performance over single-core processors for independent parallel tasks nearly linearly as long as the memory bandwidth is sufficient. Speedup is, however, difficult to find when dense intercommunication between the cores is required. This forces programmers to use more complex and error-prone programming techniques instead of straight-forward parallel processing patterns. To solve these problems, we have introduced the Thick Control Flow (TCF) Processor Architecture (TPA). TCF is an abstraction of parallel computation that combines self-similar threads into computational entities. While there are already a number of performance studies for TPA, it is not known how well TPA performs against commercial multicores. In this paper, we compare the performance and programmability of TPA and Intel Skylake multicore CPUs with kernel programs. Code examples and qualitative observations on the included programming approaches are given.