Reconfigurable Computing

Reconfigurable Computing has evolved to a mature level, with a wide range of applications, from high-performance to embedded computing domains. The research community has witnessed exciting advancements, promoted by technology and scientific findings. Early stages of reconfigurable computing were dominated by the searching for killer applications. The real applications of reconfigurable computing came, in some cases as not as one expected, and widespread over almost all computing domains. However, there are still many challenges and open avenues to do research in this area and this fact makes reconfigurable computing one of the most exciting research areas related to computing!

This chapter introduces the highly promising future role of Reconfigurable Computing (RC) and emphasizes, that it is a critical survival issue for computing-supported infrastructures worldwide and stresses the urgency of moving RC from niche to mainstream. It urges acceptance of the massive challenge of reinventing computing, away from its currently obsolete CPU-processor-centric Aristotelian CS world model, over to a twin-paradigm Copernican model including and interlacing both, software and configware. It gives a flavor of the fundamentals of RC and the massive impact on the efficiency of computing it promises. Furthermore the chapter outlines the educational barriers we have to surmount and the urgent need for major funding on a global scale to run a world-wide mass movement, of a dimension at least as far reaching as the Mead-&-Conway-style VLSI design revolution in the early 1980s. The scenarios are similar: around 1980 an urgently needed designer population has been missing. Now a properly qualified programmer population is not existing. But this time the scenario is much more complex and the problem is more difficult, requiring not only a twin-paradigm approach for programming heterogeneous systems including both: many-core processors and reconfigurable accelerators, but also to find a solution to the parallelism crisis also called the “Programming wall”. The presentation of recent R&D advances in RC, especially those ones funded by the EU, are also subject of all other chapters of this book.

The new developments in semiconductor technology cause significant problems in chips’ performance, power consumption and reliability, indicating that the “golden” CMOS era is long gone. Technology scaling does not deliver anymore significant performance speedup, the increasing power density poses severe limitations in chips, while, transistors become less reliable. The above introduce great challenges for reconfigurable computing; that is to provide the answer to the performance, power-efficiency and reliability quest posed by current technology trends. Reconfigurable Computing has the potential to achieve such a goal; however, ­several improvements are required to be performed first. In this chapter, we discuss a number of issues which need to be addressed in order to make Reconfigurable Computing a widely used solution for future systems.

The exponential increase of CMOS circuit complexity has opened the way to the introduction of new capabilities and functionalities into electronic systems that have been sources of innovations in major growth markets. To pursue this trend all along the last decades, major evolutions of design methodologies and ­computing architectures have been necessaries to master this complexity. Now, increasing Non-Recurrent Engineering (NRE) costs have made the design of ASICs or System-on-Chips unaffordable for a broad class of applications, whose the low-volume markets are insufficient to make them economically viable. But, use of Commercial Off-The-Shelf (COTS) boards is not always satisfactory due to the low power-efficiency of general-purpose processors and the complexity of programming FPGAs. We thus advocate for a new class of System-on-Chips, composed of a mix of processors as well as very flexible and easily programmable accelerators in order to cope with increasing NRE costs and tight time-to-markets. In this perspective, reconfigurable architectures are very appealing for their trade-off between the performance of ASICs and the flexibility of general-purpose processors. This chapter presents an innovative approach of a dynamically reconfigurable heterogeneous platform, called MORPHEUS and which consists of a System-on-Chip integrating different kinds of reconfigurable accelerators controlled by a general-purpose processor.

When targeting heterogeneous, multi-core platforms, system and application developers are not only confronted with the challenge of choosing the best hardware configuration for the application they need to map, but also the application has to be modified such that certain parts are executed on the most appropriate hardware component. The hArtes toolchain provides (semi) automatic support to the designer for this mapping effort. A hardware platform was specifically designed for the project, which consists of an ARM processor, a DSP and an FPGA. The ­toolchain, targeting this platform but potentially targeting any similar system, has been tested and validated on several computationally intensive applications and resulted in substantial speedups as well as drastically reduced development times. We report speedups of up to nine times compared against a pure ARM based execution, and mapping can be done in minutes. The toolchain thus allows for easy design space exploration to find the best mapping, given hardware availability and real time execution constraints.

The overall mission of the 4S project (Smart Chips for Smart Surroundings) was to define and develop efficient flexible, reconfigurable core building blocks, including the supporting tools, for future Ambient System Devices. Reconfigurability offers the needed flexibility and adaptability, it provides the efficiency needed for these systems, it enables systems that can adapt to rapidly changing environmental conditions, it enables communication over heterogeneous wireless networks, and it reduces risks: reconfigurable systems can adapt to standards that may vary from place to place or standards that have changed during and after product development. In 4S we focused on heterogeneous building blocks such as analogue, hardwired functions, fine and coarse grain reconfigurable tiles and microprocessors. Such a platform can adapt to a wide application space without the need for specialized ASICs. A novel power aware design flow and runtime system was developed. The runtime system decides dynamically about the near-optimal application mapping to the given hardware platform. The overall concept was verified on hardware platforms based on an existing SoC and in a second step with novel silicon. DRM (Digital Radio Mondiale) and MPEG4 Video applications have been implemented on the platforms demonstrating the adaptability of the 4S concept.

The ÆTHER project has laid the foundation of a complete new framework for designing and programming computing resources that live in changing ­environments and need to re-configure their objectives in a dynamic way. This chapter contributes to a strategic research agenda in the field of self-adaptive computing systems. It brings inputs to the reconfigurable hardware community and proposes directions to go for reconfigurable hardware and research on self-adaptive computing; it tries to identify some of the most promising future technologies for reconfiguration, while pointing out the main foreseen Challenges for reconfigurable hardware. This chapter presents the main solutions the ÆTHER project proposed for some of the major concerns in trying to engineer a self-adaptive computing system. The text exposes the ÆTHER vision of self-adaptation and its requirements. It describes and discusses the proposed solutions for tackling self-adaptivity at the various levels of abstractions. It exposes how the developed technologies could be put together in a real methodology and how self-adaptation could then be used in potential applications. Finally and based on lessons learned from ÆTHER, we discuss open issues and research opportunities and put those in perspective along other investigations and roadmaps.

The main objective of the here presented ANDRES project is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES). Based on a domain-independent formal foundation we combine domain-specific modelling languages and libraries into an integrated framework. This framework allows efficiently using and exploiting adaptivity in embedded systems. The design flow is completed by a methodology for performance analysis and tools for the automatic synthesis of adaptive hardware/software systems.

The Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project aims to create a highly scalable and dependable reconfigurable system concept for a wide range of tomorrow’s streaming DSP applications. Within CRISP, a network-on-chip based many-core stream processor with dependability infrastructure and run-time resource management is devised, implemented, and manufactured to demonstrate a coarse-grained core-level reconfigurable system with scalable computing power, flexibility, and dependability. This chapter introduces CRISP, presents the concepts, and outlines the preliminary results of a running project.

In a scenario where the complexity and diversity of embedded systems is rising and causing extra pressure in the demand for performance at the lowest ­possible power budget, designers face the challenge brought by the power and memory walls in the production of embedded platforms. The focus of the ERA project is to investigate and propose new methodologies in both tools and hardware design to break through these walls, and help design the next-generation embedded systems platforms. The proposed strategy is to utilize adaptive hardware to provide the highest possible performance with limited power budgets. The envisioned adaptive platform employs a structured design approach that allows integration of ­varying computing elements, networking elements, and memory elements. For computing elements, ERA utilizes a mixture of commercially available off-the-shelf processor cores, industry-owned IP cores, and application-specific/dedicated cores. These are dynamically adapted regarding their composition, organization, and even instruction-set architectures, to provide the best possible performance/power trade-offs. Similarly, the choice of the most-suited network elements and topology and the adaptation of the hierarchy and organization of the memory elements can be determined at design-time or at run-time. Furthermore, the envisioned adaptive platform must be supported by and/or made visible to the application(s), run-time system, operating system, and compiler, exploiting the synergism between software and hardware. Having the complete freedom to flexibly tune the hardware elements allows for a much higher level of efficiency, riding the trade-off curve between ­performance and power compared to the state of the art. An additional goal of the adaptive platform is to serve as a quick prototyping platform in embedded systems design.

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) has made them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved very often at unreasonably high design efforts. This project covers developing, implementing and evaluating a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented Specifications to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development as well as program and application portability. We leverage Aspect-Oriented specifications and a set of transformations to generate an intermediate representation suitable to hardware mapping. A programming language, LARA, will allow the exploration of alternative architectures and design patterns enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio processing and real-time avionics. We expect the technology developed in REFLECT to be integrated by our industrial partners, in particular by ACE, a leading compilation tool supplier for embedded systems, and by Honeywell, a worldwide solution supplier of embedded high-performance systems.

Although the maturity level already achieved, Reconfigurable Computing is far from being completely exploited. Becoming increasingly important also makes reconfigurable computing technology very attractive and interesting. The interests come from diverse areas of computing, from embedded to high-performance computing, and from various domains of applications. Recognizing the importance of reconfigurable computing, the EU (European Union) funded, through its framework programs, a number of research projects during recent years.