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GraphScSh: Efficient I/O Scheduling and Graph Sharing for Concurrent Graph Processing Read chapter Read first chapter

2019 | OriginalPaper | Chapter

SIRM: Shift Insensitive Racetrack Main Memory

Authors : Hongbin Zhang, Bo Wei, Youyou Lu, Jiwu Shu

Published in: Network and Parallel Computing

Publisher: Springer International Publishing

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Abstract

Racetrack memory (RM) is a potential DRAM alternative due to its high density and low energy cost and comparative access latency with SRAM. On this occasion, we propose a shift insensitive racetrack main memory architecture SIRM. SIRM provides uniform access latency to upper system, which make it easy to be managed. Experiments demonstrate that RM can outperform DRAM for main memory design with higher density and energy efficiency.

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previous chapter DAFL: Deep Adaptive Feature Learning for Network Anomaly Detection
next chapter PDRM: A Probability Distribution Based Resource Management for Batch Workloads in Heterogeneous Cluster
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Metadata
Title
SIRM: Shift Insensitive Racetrack Main Memory
Authors
Hongbin Zhang
Bo Wei
Youyou Lu
Jiwu Shu
Copyright Year
2019
Book
Network and Parallel Computing

Print ISBN: 978-3-030-30708-0

Electronic ISBN: 978-3-030-30709-7

Copyright Year: 2019

DOI
https://doi.org/10.1007/978-3-030-30709-7_33

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