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Published in:
System-on-a-Chip Design Read chapter Read first chapter

2014 | OriginalPaper | Chapter

5. SoC Design Methodology

Authors : Roopak Sinha, Parthasarathi Roop, Samik Basu

Published in: Correct-by-Construction Approaches for SoC Design

Publisher: Springer New York

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Abstract

Chapter 5 provides an SoC design approach, where on-chip protocols are described as SKS and requirements are captured as boiler plates. It then develops an approach called oversampling to bridge the clock mismatches between IPs. Finally, it uses an approach based on “converter synthesis” to propose the design methodology. The concepts in this chapter are illustrated using a set-top box example. This chapter may be viewed as the “correct-by-construction design methodology” chapter.

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previous chapter Models for SoCs and Specifications
next chapter Automatic Protocol Conversion
Literature
[CT92]
J.C. Candy, G.C. Temes, Oversampling methods for a/d and d/a conversion. Oversampling Delta-Sigma Data Converters ( IEEE Press, New York, 1992), pp. 1–25
[CP03]
J.-L. Colaço, M. Pouzet, Clocks as first class abstract types. In EMSOFT, ed. by R. Alur, I. Lee. Lecture Notes in Computer Science, vol 2855 (Springer, New York, 2003), pp. 134–155
[PdAHSV02]
R. Passerone, L. de Alfaro, T.A. Henzinger, A.L. Sangiovanni-Vincentelli, Convertibility verification and converter synthesis: two faces of the same coin. In International Conference on Computer Aided Design ICCAD, 2002
[SRBS09]
R. Sinha, P.S. Roop, S. Basu, Z. Salcic, Multi-clock SoC design using protocol conversion. In Design and Test Europe (DATE) (IEEE, New York, 2009), pp. 123–128
Metadata
Title
SoC Design Methodology
Authors
Roopak Sinha
Parthasarathi Roop
Samik Basu
Copyright Year
2014
Publisher
Springer New York
Book
Correct-by-Construction Approaches for SoC Design

Print ISBN: 978-1-4614-7863-8

Electronic ISBN: 978-1-4614-7864-5

Copyright Year: 2014

DOI
https://doi.org/10.1007/978-1-4614-7864-5_5