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2016 | OriginalPaper | Chapter

Static Verification of Railway Schema and Interlocking Design Data

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Abstract

The paper presents an experience of verifying a large scale, real-life dataset describing various aspects of railway station design. We discuss how a number of assorted digital artefacts were pooled together and converted into a set-theoretic model over which a type inference procedure is run. The typed model is then used to confirm or contradict logical conjectures over data elements. We employ a number of state-of-the-art SMT solvers as a verification back-end. The project is ongoing but has already identified a number of issues in topology definition and signalling data that were missed by other automated tests and not revealed by simulation tools.

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Metadata
Title
Static Verification of Railway Schema and Interlocking Design Data
Authors
Alexei Iliasov
Paulius Stankaitis
David Adjepon-Yamoah
Copyright Year
2016
DOI
https://doi.org/10.1007/978-3-319-33951-1_9

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