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2018 | OriginalPaper | Chapter

Synthesis of High-Speed ASM Controllers with Moore Outputs by Introducing Additional States

Authors : Valery Salauyou, Irena Bulatowa

Published in: Computer Information Systems and Industrial Management

Publisher: Springer International Publishing

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Abstract

In the paper, we propose a new method for FPGA-based design of high-speed Algorithmic State Machine (ASM) controllers. The method is based on the introduction of additional states of the state machine in order to implement all transition functions in the single-level structures. In this method, such an optimization criterion as a critical path delay is applied already at the stage of converting the ASM chart to the state machine HDL description. The proposed method consists of two steps: determining the place of additional labels on the ASM chart and introducing additional states of FSM. Experimental results show that our approach achieves an average performance gain of 20.43% to 27.41% (for various FPGA devices) compared with the traditional synthesis method. The maximum performance increase achieved is 59.17%. At the same time, the method slightly increases the cost of implementation by an average of 5.13% to 5.19%, but in some cases even reduces the cost.

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Literature
1.
go back to reference Glushkov, V.: Automaton theory and formal microprogram transformation. Cybernetics 1, 1–8 (1968)CrossRef Glushkov, V.: Automaton theory and formal microprogram transformation. Cybernetics 1, 1–8 (1968)CrossRef
2.
go back to reference Clare, C.: Designing Logic Systems Using the State Machines. McGraw-Hill, New York (1973) Clare, C.: Designing Logic Systems Using the State Machines. McGraw-Hill, New York (1973)
3.
go back to reference Green, D.H., Chughtai, M.A.: Use of multiplexers in the direct synthesis of ASM-based designs. IEEE Proc. E, Comput. Digit. Tech. 133(4), 194–200 (1986) Green, D.H., Chughtai, M.A.: Use of multiplexers in the direct synthesis of ASM-based designs. IEEE Proc. E, Comput. Digit. Tech. 133(4), 194–200 (1986)
4.
go back to reference Baranov, S.: Logic Synthesis for Control Automata. Kluwer Academic Publisher, Boston (1994)CrossRef Baranov, S.: Logic Synthesis for Control Automata. Kluwer Academic Publisher, Boston (1994)CrossRef
5.
go back to reference Lu, J.Y., Kim, J.D., Chin, S.K.: Hardware composition with hardware flowcharts and process algebras. In: 2nd IEEE International Conference on Engineering of Complex Computer Systems Proceedings, pp. 352–364. IEEE, Montreal, Canada (1996) Lu, J.Y., Kim, J.D., Chin, S.K.: Hardware composition with hardware flowcharts and process algebras. In: 2nd IEEE International Conference on Engineering of Complex Computer Systems Proceedings, pp. 352–364. IEEE, Montreal, Canada (1996)
6.
go back to reference Baranov, S.: Minimization of algorithmic state machines. In: 24th Euromicro Conference Proceedings, pp. 176–179. IEEE, Vasteras, Sweden (1998) Baranov, S.: Minimization of algorithmic state machines. In: 24th Euromicro Conference Proceedings, pp. 176–179. IEEE, Vasteras, Sweden (1998)
7.
go back to reference Levin, I., Sinelnikov, V., Karpovsky, M.: Synthesis of ASM-based self-checking controllers. In: Euromicro Symposium on Digital Systems Design Proceedings, pp. 87–93. IEEE, Warsaw, Poland (2001) Levin, I., Sinelnikov, V., Karpovsky, M.: Synthesis of ASM-based self-checking controllers. In: Euromicro Symposium on Digital Systems Design Proceedings, pp. 87–93. IEEE, Warsaw, Poland (2001)
8.
go back to reference De Pablo, S., Cáceres, S., Cebrián, J.A., Berrocal, M.: A proposal for ASM ++ diagrams. In: Design and Diagnostics of Electronic Circuits and Systems Proceedings, pp. 1–4. IEEE, Krakow, Poland (2007) De Pablo, S., Cáceres, S., Cebrián, J.A., Berrocal, M.: A proposal for ASM ++ diagrams. In: Design and Diagnostics of Electronic Circuits and Systems Proceedings, pp. 1–4. IEEE, Krakow, Poland (2007)
9.
go back to reference Barkalov, A., Titarenko, L., Bieganowski, J.: Reduction in the number of LUT elements for control units with code sharing. Int. J. Appl. Math. Comput. Sci. 20(4), 751–761 (2010)CrossRef Barkalov, A., Titarenko, L., Bieganowski, J.: Reduction in the number of LUT elements for control units with code sharing. Int. J. Appl. Math. Comput. Sci. 20(4), 751–761 (2010)CrossRef
11.
go back to reference Hertwig, A., Wunderlich, H.: Fast controllers for data dominated applications. In: European Design and Test Conference (ED & TC 1997) Proceedings, pp. 84–89. IEEE, Paris, France (1997) Hertwig, A., Wunderlich, H.: Fast controllers for data dominated applications. In: European Design and Test Conference (ED & TC 1997) Proceedings, pp. 84–89. IEEE, Paris, France (1997)
12.
go back to reference Czerwinski, R., Kania, D.: State assignment and optimization of ultra-high-speed FSMs utilizing tristate buffers. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 22(1) (2016). Article 3 Czerwinski, R., Kania, D.: State assignment and optimization of ultra-high-speed FSMs utilizing tristate buffers. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 22(1) (2016). Article 3
13.
go back to reference Kim, E., Lee, D., Saito, H., Nakamura, H., Lee, J., Nanya, T.: Performance optimization of synchronous control units for datapaths with variable delay arithmetic units. In: ASP-DAC Asia and South Pacific Design Automation Conference Proceedings, pp. 816–819. IEEE, Kitakyushu (2003) Kim, E., Lee, D., Saito, H., Nakamura, H., Lee, J., Nanya, T.: Performance optimization of synchronous control units for datapaths with variable delay arithmetic units. In: ASP-DAC Asia and South Pacific Design Automation Conference Proceedings, pp. 816–819. IEEE, Kitakyushu (2003)
14.
go back to reference Weng, S., Kuo, Y., Chang, S.: Timing optimization in sequential circuit by exploiting clock-gating logic. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 17(2) (2012). Article 16 Weng, S., Kuo, Y., Chang, S.: Timing optimization in sequential circuit by exploiting clock-gating logic. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 17(2) (2012). Article 16
15.
go back to reference Bommu, S., O’Neill, N., Ciesielski, M.: Retiming-based factorization for sequential logic optimization. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 5(3), 373–398 (2000)CrossRef Bommu, S., O’Neill, N., Ciesielski, M.: Retiming-based factorization for sequential logic optimization. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 5(3), 373–398 (2000)CrossRef
16.
go back to reference Huang, S.: On speeding up extended finite state machines using catalyst circuitry. In: ASP-DAC 2001 Asia and South Pacific Design Automation Conference (DAC 2006) Proceedings, pp. 583–588. IEEE, Yokohama (2001) Huang, S.: On speeding up extended finite state machines using catalyst circuitry. In: ASP-DAC 2001 Asia and South Pacific Design Automation Conference (DAC 2006) Proceedings, pp. 583–588. IEEE, Yokohama (2001)
17.
go back to reference Gupta, G.R., Gupta, M., Panda, P.R.: Rapid estimation of control delay from high-level specifications. In: 43rd Design Automation Conference Proceedings, pp. 455–458. ACM, San Francisco, USA (2010) Gupta, G.R., Gupta, M., Panda, P.R.: Rapid estimation of control delay from high-level specifications. In: 43rd Design Automation Conference Proceedings, pp. 455–458. ACM, San Francisco, USA (2010)
18.
go back to reference Salauyou, V., Klimowicz, A., Grzes, T., Bulatowa, I., Dimitrowa-Grekow, T.: Synthesis methods of finite state machines implemented in package ZUBR. In: 6th International Conference Computer-Aided Design of Discrete Devices (CAD DD2007) Proceedings, pp. 53–56. National Academy of Sciences of Belarus, Minsk (2007) Salauyou, V., Klimowicz, A., Grzes, T., Bulatowa, I., Dimitrowa-Grekow, T.: Synthesis methods of finite state machines implemented in package ZUBR. In: 6th International Conference Computer-Aided Design of Discrete Devices (CAD DD2007) Proceedings, pp. 53–56. National Academy of Sciences of Belarus, Minsk (2007)
Metadata
Title
Synthesis of High-Speed ASM Controllers with Moore Outputs by Introducing Additional States
Authors
Valery Salauyou
Irena Bulatowa
Copyright Year
2018
DOI
https://doi.org/10.1007/978-3-319-99954-8_34

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