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2017 | OriginalPaper | Chapter

Testing of Embedded SRAMs Using Parasitic Extraction Method

Authors : Muddapu Parvathi, K. Satya Prasad, N. Vasantha

Published in: 9th International Conference on Robotic, Vision, Signal Processing and Power Applications

Publisher: Springer Singapore

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Abstract

The limitation with the existing testing techniques is, if the test does not consider all the aspects of SRAM parameters, including parasitic memory effect, then it will result as an incomplete test. This paper presents a new parasitic extraction testing method for embedded SRAMs, employing defect-induced layout. The defect injection in a circuit is due to an open/short between wires, or missing contacts etc. In this work, only node-to-node short defects are considered. Our test results proved that using parasitic extraction method existing faults as well as undefined faults could be detected. The existing faults identified are Stuck At Fault, (SAF), Undefined Read Fault (URF), Read Destructive Fault (RDF), Undefined Write Fault (UWF), Random Read Fault (RRF), Incorrect Read Fault (IRF), and No Access Fault (NAF). The undefined faults identified are Bit-Line Delay Fault (BDF), Initialization Order Fault (IOF), Un Stabilized Write Fault (USWF), Un Stabilized Read Fault (USRF), and Write Before Access Fault (WBAF). In addition, the complete fault model dictionary is also an outcome of this work.

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Literature
1.
go back to reference International Technology Roadmap for Semiconductors, 2013 edn, Executive Summary. International Technology Roadmap for Semiconductors, 2013 edn, Executive Summary.
2.
go back to reference Segura J, Rubio A (1997) A detailed analysis of CMOS SRAM’s with gate oxide short defects. IEEE J. Solid-State Circ. 32(10) Segura J, Rubio A (1997) A detailed analysis of CMOS SRAM’s with gate oxide short defects. IEEE J. Solid-State Circ. 32(10)
3.
go back to reference Pavlov A, Sachdev M, de Gyvez JP An SRAM weak cell fault model and a DFT technique with a programmable detection threshold. In: ITC’04 proceedings of the international test conference on international test conference, pp 1006–1015, ISBN:0-7803-8581-0 Pavlov A, Sachdev M, de Gyvez JP An SRAM weak cell fault model and a DFT technique with a programmable detection threshold. In: ITC’04 proceedings of the international test conference on international test conference, pp 1006–1015, ISBN:0-7803-8581-0
4.
go back to reference Majhi AK, Azimane M, Eichenberger S, Bowen F Memory testing under different stress conditions: an industrial evaluation. In: Proceedings of the design, automation and test in Europe conference and exhibition (DATE’05) 1530–1591/05 IEEE Majhi AK, Azimane M, Eichenberger S, Bowen F Memory testing under different stress conditions: an industrial evaluation. In: Proceedings of the design, automation and test in Europe conference and exhibition (DATE’05) 1530–1591/05 IEEE
5.
go back to reference Dilillo L, Girard P, Pravossoudovitch S, Virazel A (2005) Efficient marchtest procedure for dynamic read destructive fault detection in SRAM memories. J Electron Test 21(5):551–561CrossRef Dilillo L, Girard P, Pravossoudovitch S, Virazel A (2005) Efficient marchtest procedure for dynamic read destructive fault detection in SRAM memories. J Electron Test 21(5):551–561CrossRef
6.
go back to reference Benso A, Bosio A, Di Carlo S, Di Natale G, Prinetto P (2008) March test generation revealed. IEEE Trans Comput 57(12) Benso A, Bosio A, Di Carlo S, Di Natale G, Prinetto P (2008) March test generation revealed. IEEE Trans Comput 57(12)
7.
go back to reference Fonseca RA, Dilillo1 L, Bosio A, Girard P, Pravossoudovitch S, Virazel A, Badereddine N Analysis of resistive-bridging defects in SRAM core-cells: a comparative study from 90 nm down to 40 nm technology nodes*. 978-1-4244-5833- 2/10/2010 IEEE Fonseca RA, Dilillo1 L, Bosio A, Girard P, Pravossoudovitch S, Virazel A, Badereddine N Analysis of resistive-bridging defects in SRAM core-cells: a comparative study from 90 nm down to 40 nm technology nodes*. 978-1-4244-5833- 2/10/2010 IEEE
8.
go back to reference Hsu C-L, Ho M-H, Lin C-F (2009) Novel built-in current-sensor-based IDDQ testing scheme for CMOS integrated circuits. IEEE Trans Instrum Meas 58(7) Hsu C-L, Ho M-H, Lin C-F (2009) Novel built-in current-sensor-based IDDQ testing scheme for CMOS integrated circuits. IEEE Trans Instrum Meas 58(7)
10.
go back to reference Lin C-W, Chen H-H, Yang H-Y, Huang C-Y, Chao MC-T, Huang R-F (2013) Fault models and test methods for sub threshold SRAMs. IEEE Trans Comput 62(3) Lin C-W, Chen H-H, Yang H-Y, Huang C-Y, Chao MC-T, Huang R-F (2013) Fault models and test methods for sub threshold SRAMs. IEEE Trans Comput 62(3)
11.
go back to reference Sachdev M, de Gyvez JP Defect-oriented testing for nano-metric CMOS VLSI circuits, 2nd edn. University of Waterloo Ontario, Canada Sachdev M, de Gyvez JP Defect-oriented testing for nano-metric CMOS VLSI circuits, 2nd edn. University of Waterloo Ontario, Canada
12.
go back to reference Van de Goor AJ (2004) Using march tests to test SRAMs. IEEE Des Test Comput 10(1):8–14 Van de Goor AJ (2004) Using march tests to test SRAMs. IEEE Des Test Comput 10(1):8–14
13.
go back to reference Dekker R, Beenker F, Thijssen L (1990) A realistic fault model and test algorithms for static random access memories. IEEE Trans Comput-Aided Des 9(6) Dekker R, Beenker F, Thijssen L (1990) A realistic fault model and test algorithms for static random access memories. IEEE Trans Comput-Aided Des 9(6)
14.
go back to reference Joshi RV, Mukhopadhyay S, Plass DW, Chan YH, Chuang C-T, Tan Y (2009) Design of sub-90 nm low-power and variation tolerant PD/SOI SRAM cell based on dynamic stability metrics. IEEE J Solid-State Circuits 44(3):965–976. doi:10.1109/JSSC.2009.2013768. 0018-9200/2009 IEEE Joshi RV, Mukhopadhyay S, Plass DW, Chan YH, Chuang C-T, Tan Y (2009) Design of sub-90 nm low-power and variation tolerant PD/SOI SRAM cell based on dynamic stability metrics. IEEE J Solid-State Circuits 44(3):965–976. doi:10.​1109/​JSSC.​2009.​2013768. 0018-9200/2009 IEEE
16.
go back to reference Segura J, Rubio A (1997) A detailed analysis of CMOS SRAM’s with gate oxide short defects. IEEE J Solid-State Circuits 32(10):1543–1550. 0018-9200/97 IEEE, 0018-9200(97)06314-2 Segura J, Rubio A (1997) A detailed analysis of CMOS SRAM’s with gate oxide short defects. IEEE J Solid-State Circuits 32(10):1543–1550. 0018-9200/97 IEEE, 0018-9200(97)06314-2
17.
go back to reference Hsu CL, Ho MH, Lin CF (2009) Novel built-in current sensor based IDDQ testing scheme for CMOS integrated circuits. IEEE Trans Instrum Meas 58(7):2196–2208. doi:10.1109/TIM.2009.2013668. 0018-9456/2009 IEEE Hsu CL, Ho MH, Lin CF (2009) Novel built-in current sensor based IDDQ testing scheme for CMOS integrated circuits. IEEE Trans Instrum Meas 58(7):2196–2208. doi:10.​1109/​TIM.​2009.​2013668. 0018-9456/2009 IEEE
18.
go back to reference Irobi S, Al-Ars Z, Hamdioui S, Thibeault C (2011) Testing for parasitic memory effect in SRAMs. In: Test symposium (ATS), 2011, 20th Asian, 978-1-4577-1984-4, 0.1109/ATS.2011.76, IEEE Irobi S, Al-Ars Z, Hamdioui S, Thibeault C (2011) Testing for parasitic memory effect in SRAMs. In: Test symposium (ATS), 2011, 20th Asian, 978-1-4577-1984-4, 0.1109/ATS.2011.76, IEEE
19.
go back to reference Parvathi M, Vasantha N, Prasad KS (2013) Fault model analysis by parasitic extraction method for embedded SRAM. Int J Res Eng Technol 02(12) Parvathi M, Vasantha N, Prasad KS (2013) Fault model analysis by parasitic extraction method for embedded SRAM. Int J Res Eng Technol 02(12)
20.
go back to reference Parvathi M, Vasantha N, Prasad KS (2015) New fault model analysis for embedded SRAM cell for deep submicron technologies using parasitic extraction method. In: 2015 international conference on VLSI systems, architecture, technology and applications (VLSI-SATA), pp 125–130. 978-1-4799-7926-4/15 Parvathi M, Vasantha N, Prasad KS (2015) New fault model analysis for embedded SRAM cell for deep submicron technologies using parasitic extraction method. In: 2015 international conference on VLSI systems, architecture, technology and applications (VLSI-SATA), pp 125–130. 978-1-4799-7926-4/15
Metadata
Title
Testing of Embedded SRAMs Using Parasitic Extraction Method
Authors
Muddapu Parvathi
K. Satya Prasad
N. Vasantha
Copyright Year
2017
Publisher
Springer Singapore
DOI
https://doi.org/10.1007/978-981-10-1721-6_6