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2013 | OriginalPaper | Chapter

3. Transistor Aging Compact Modeling

Authors : Elie Maricau, Georges Gielen

Published in: Analog IC Reliability in Nanometer CMOS

Publisher: Springer New York

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Abstract

The focus of this work is on simulation and analysis of the impact of transistor aging on ICs integrated in nm CMOS processes. Accurate circuit simulation starts with the availability of good transistor compact models. This chapter therefore discusses the development of a set of models for simulation of the most important aging effects.

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previous chapter CMOS Reliability Overview
next chapter Background on IC Reliability Simulation
Footnotes
1
A base different from 10 can also be used and would alter the model parameters, but it would not affect the overall behavior of the model.
 
2
One can proof that, when adding a small correction factor, Eq. (3.45) is also valid for \(\xi \in \mathbb{R }\), but for the sake of simplicity, this is not included here.
 
3
The constant equal to 0.19 results from factor \(A\) in Eq. (3.46).
 
4
When analyzing circuits with transistors that are stressed near or above the nominal supply voltage for an extended period of time, a more complex model has to be used. Such models have been discussed in Sect. 3.4.
 
Metadata
Title
Transistor Aging Compact Modeling
Authors
Elie Maricau
Georges Gielen
Copyright Year
2013
Publisher
Springer New York
Book
Analog IC Reliability in Nanometer CMOS

Print ISBN: 978-1-4614-6162-3

Electronic ISBN: 978-1-4614-6163-0

Copyright Year: 2013

DOI
https://doi.org/10.1007/978-1-4614-6163-0_3