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2011 | OriginalPaper | Chapter

7. Translation Validation of High-Level Synthesis

Authors : Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta

Published in: High-Level Verification

Publisher: Springer New York

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Abstract

Once the important properties of the high-level components have been verified possibly using techniques presented in Chaps. 5 and 6, the translation from the high-level design to low-level RTL still needs to be proven correct, thereby also guaranteeing that the important properties of the components are preserved. In this chapter we will discuss an approach that proves that the translation from high-level design to a scheduled design is correct, for each translation that the HLS tool performs. In the next chapter we will describe another approach that will allow us to write part of these tools in a provably correct manner.

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previous chapter Bounded Model Checking for Concurrent Systems: Synchronous Vs. Asynchronous
next chapter Parameterized Program Equivalence Checking
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Metadata
Title
Translation Validation of High-Level Synthesis
Authors
Sudipta Kundu
Sorin Lerner
Rajesh K. Gupta
Copyright Year
2011
Publisher
Springer New York
Book
High-Level Verification

Print ISBN: 978-1-4419-9358-8

Electronic ISBN: 978-1-4419-9359-5

Copyright Year: 2011

DOI
https://doi.org/10.1007/978-1-4419-9359-5_7