VLSI Implementation of Artificial Neural Network

In this work, VLSI circuit-based artificial neural network has been implemented. The artificial neuron consists of three components such as multiplier, adder and neuron active function circuit, which perform arithmetic operations for realizing neural network. The focus on this work is linearity investigation in nonlinear artificial neural network as well as learning efficiency. A multiplier design has been proposed for reducing nonlinearity in an artificial neuron. Sigmoid circuit has been used for activation function. New weight update technique with both retrieving and on chip learning function has been proposed for better accuracy and improved learning ability. In this neural network, pulse width modulation technique has been used to compute the output signals using both multiplication and summation operations. This improves the linearity of the neural network. The learning operation of the neural network has been verified through simulation results by adopting digital function like “NAND”. A high-speed and accurate error detection block has also been used for this purpose. Cadence Virtuoso has been used to perform circuit level simulation. Design has been done in TSMC 180 nm CMOS technology. In the proposed design, an error calculation time of 0–100 ps has been achieved, thereby making the overall operation fast and the learning efficiency 99%. Supply voltage is 1.8 V, and total power dissipation has been measured to be is 8 mW.