Wafer-Level Chip-Scale Packaging

A review of recent advances in analog and power wafer-level chip-scale packaging (WLCSP) is presented based on the development and market demand in semiconductor industry. This chapter covers in more detail how advances in both the analog and power advanced wafer-level package fan-in/fan-out design and 3D integration have co-enabled significant advances in analog and power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in techniques of analog, power switches, and passives can drive continued enhancements in usability, efficiency, reliability, and overall cost of analog and power semiconductor solutions. Challenges of die shrinkage in both wafer-level analog and power semiconductor packaging in next-generation design are presented and discussed.

Fan-in wafer-level chip-scale package is the first form of WLCSP. The term “fan-in” comes from the fact that early time WLCSP was originally designed as wire bond devices with bond pads all arranged along the perimeters of semiconductor dies. When converting a perimeter bond pad design into an area array WLCSP, redistribution or “fan-in” technology had to be used.

The concept of fan-out is hardly new for semiconductor packaging. Ever since the early days of semiconductor industry, fan-out scheme that expands the tight lead pitch on semiconductor to coarse lead pitch on package is the dominant form in all chip packages, for example, leadframe package fan-out from chip to leads via bonding wires and flip chip package fan-out from chip to BGA via inner metal layers in the substrate (Fig. 3.1a, b).

Stacking is a trend that has brought and still brings excitements to the semiconductor packaging societies. While the main driving force for the stacked package has been high level of integration and smaller package footprint, improvement of electrical performance due to the shortened path of signal transmission and power distribution is also frequently referred. Though it is relatively rare, improvement of overall thermal performance is occasionally mentioned as well. More frequently, heat dissipation is one of the mostly concerned areas for the stacked package. Cost of manufacturing the 3D structure seems to be the main hurdle for wider adoptions of the more aggressive 3D package concepts.

Discrete power device is one of the basic units that fuel the power management and conversion in various applications. Typical discrete products include various diodes, bipolars, metal–oxide semiconductor field-effect transistors (Mosfets), and insulated gate bipolar transistor (IGBTs). As the needs of miniaturization, one trend of the discrete power Mosfet packages is to move the discrete power devices into various wafer-level chip-scale package for better surface amount purpose. Since power levels and power density requirements continue to increase for many types of end equipment such as personal computers, servers, network, and telecom systems, it demands higher performance from the components that make up the power management system. This chapter introduces the design of discrete power package and the analysis of the wafer-level discrete power package performance.

The development of the analog and power IC package is a dynamic technology. Both analog and power IC WLCSP applications that were unattainable only a few years ago are today commonplace thanks in part to advances in WLCSP electronic package design. From portable applications such as in mobile telecommunications to consumer electronics, each imposes its own individual demands on the development of WLCSP. To meet such a diverse range of application requirements, WLCSP range encompasses from pure analog application, power application, and system-on-chip (SOC) integration of analog, logic, mixed signal, and power device to system in package which includes individual analog, logic, and power devices, most of which are subdivided into a number of outline versions of wafer-level packaging. The analog and power WLCSP offers a high thermal dissipation enabling analog and power IC usage in some of the most demanding application areas which integrate analog, logic, and power mosfets with through-silicon via (TSV), stack die technology [1, 2]. This chapter will introduce the development of the advanced wafer-level packaging with TSV and stack die concepts for integration of analog and power solutions.

The operation of a wafer-level semiconductor device is sensitive to junction temperature. When the junction temperature exceeds the functional limit, the device does not operate in a normal way. It is also well known that the failure rates of semiconductor devices increase exponentially as the junction temperature rises. Figure 7.1 shows a FLIR camera image of temperature distribution inside a smart phone, which gives the sources of heat dissipation from WLCSPs mounted on the board. It is very crucial that the WLCSP designer and application engineer understand the definition, characteristics, and application of the thermal resistance of the WLCSP for proper device operation [1–6]. Power dissipation during the operation of the semiconductor device induces an increase in the junction temperature. This depends on the amount of power dissipation and the thermal resistance between the junction and the WLCSP bumps, an ambient, and some other specified reference point. This chapter introduces the thermal management, design, analysis, and cooling methods for WLCSP.

The electrical performance (such as electrical resistance, inductance, and capacitance) is a key factor for a WLCSP product. Many studies, such as the electrical performance of different devices, effect of assembly reflow process on electrical properties, and the resistance of a solder joint, have been done to improve a product’s electrical performance [1–3]. In recent years, the investigation for the electrical performance of a WLCSP has been paid more attention due to the wide applications of the WLCSP. The parasitic resistance, inductance, and capacitance (RLC) will impact the efficiency and switch speed of the WLCSP circuit. The electromigration issue of WLCSP, which is a multi-physics problem, becomes more critical due to the high current density in analog and power electronics. This chapter will introduce the electrical parasitic RLC simulation and electromigration simulation methods for WLCSP and wafer level interconnects.

Assembly of WLCSP components involves surface mounting technology (SMT), which includes pickup WLCSP components from tape and place them onto a printed circuit board (PCB), solder reflow, and optional underfill. Figure 9.1 provides a schematic diagram of a typical assembly line setup involving WLCSP, in which solder paste or flux is first printed or dispensed on the PCB respectively before WLCSP pick and placement. Reflow is followed to finish the solder joint formation between the WLCSP component(s) and PCB. Optical or X-ray inspections are arranged at various stages of assembly line to ensure correct solder paste printing (height, area, and volume of the solder paste bricks deposited on the PCB soldering pads), accurate component placement (XY offset and skewness), and proper solder joint formation. In-circuit test (ICT) is an electrical probe test on the assembled PCBs, checking for shorts, opens, resistance, capacitance, and other basic quantities which will show whether the assembly was correctly fabricated. Post solder reflow, underfill could be applied after flux clean to provide the needed protections to WLCSPs and solder joints going through subsequent assembly processing steps and to ensure robust reliability of the WLCSP devices in the everyday usage. Underfill is especially desired when die size is big or when low-K dielectrics are present in the WLCSP.

WLCSP is one of the fastest growing segments in semiconductor packaging industry due to the rapid advances in integrated circuit (IC) fabrication, small form factor, and low cost. This technology results in a lower cost per die (vs. traditional wirebond) when the die count per wafer is high. As the number of I/O per die increases (and thus the die size and the distance to neutral point increases), the WLCSP may not achieve prescribed solder joint reliability requirements; the metal stack (UBM and the Al pad), passivation, or polyimide may also appear to fail, especially when the WLCSP is mounted on the PCB. The board level reliability is a big concern for both analog and power WLCSP packaging. This chapter will discuss the WLCSP typical reliability test.