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2018 | OriginalPaper | Chapter

180-nm 20 ps Resolution 0.29 LSB Single-Shot Precision Vernier Delay Line Based Time-to-Digital Converter

Authors : R. S. S. M. R. Krishna, Debashis Jana, Sanjukta Mandal, Ashis Kumar Mal

Published in: Microelectronics, Electromagnetics and Telecommunications

Publisher: Springer Singapore

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Abstract

This article presents a Vernier Delay Line (VDL)-based Time-to-Digital Converter (TDC) in SCL 180-nm CMOS process technology. Delay elements are acknowledged through CMOS inverters and the transmission gate. Owing to vernier structure, the resolution of the TDC is that the distinction of delay lines instead of the delay of the single part. TSPC-based flip-flop uses the solitary clock and ensures to work at high frequencies with no skew. At supply voltage 1.8 V, the planned TDC demonstrates 20 ps resolution with most pessimistic scenario (PVT corners) DNL and INL of 0.3889 and 0.0032 LSB, respectively. This TDC indicates single-shot precision (\(\sigma \)) of 0.2903 LSB at an average power of 62.1936 \(\upmu \)W.

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Title: 180-nm 20 ps Resolution 0.29 LSB Single-Shot Precision Vernier Delay Line Based Time-to-Digital Converter
Authors: R. S. S. M. R. Krishna
Debashis Jana
Sanjukta Mandal
Ashis Kumar Mal
Publisher: Springer Singapore
Book: Microelectronics, Electromagnetics and Telecommunications
Print ISBN: 978-981-10-7328-1

Electronic ISBN: 978-981-10-7329-8

Copyright Year: 2018
DOI: https://doi.org/10.1007/978-981-10-7329-8_11