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2017 | OriginalPaper | Chapter

12. 3D/2.5D IC-Based Obfuscation

Authors : Yang Xie, Chongxi Bao, Ankur Srivastava

Published in: Hardware Protection through Obfuscation

Publisher: Springer International Publishing

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Abstract

Device scaling has increased interconnect power and delay to an extent that it is presenting a bottleneck to further performance gain. 3D/2.5D integration technology emerges as a viable option to improve chip performance in a direction orthogonal to costly device scaling. While the technology was originally proposed to enhance performance, it has unlocked new opportunities to thwart security threats in a global IC supply chain. Various obfuscation techniques based on 3D/2.5D IC technology have been proposed to protect IC designs from being pirated or tampered during outsourced fabrication. This chapter presents the current state of 3D/2.5D IC-based obfuscation techniques and highlights potential security opportunities and challenges of this technology in hardware intellectual property (IP) protection.

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Literature
1.
go back to reference Bao C, Forte D, Srivastava A (2014) On application of one-class SVM to reverse engineering-based hardware trojan detection. In: 2014 15th International symposium on quality electronic design (ISQED). IEEE, New York, pp 47–54 Bao C, Forte D, Srivastava A (2014) On application of one-class SVM to reverse engineering-based hardware trojan detection. In: 2014 15th International symposium on quality electronic design (ISQED). IEEE, New York, pp 47–54
2.
go back to reference Bao C, Forte D, Srivastava A (2015) Temperature tracking: toward robust run-time detection of hardware trojans. IEEE Trans Comput-Aided Des Integr Circuits Syst 34(10):1577–1585CrossRef Bao C, Forte D, Srivastava A (2015) Temperature tracking: toward robust run-time detection of hardware trojans. IEEE Trans Comput-Aided Des Integr Circuits Syst 34(10):1577–1585CrossRef
3.
go back to reference Baumgarten A, Tyagi A, Zambreno J (2010) Preventing ic piracy using reconfigurable logic barriers. IEEE Des Test Comput 27(1):66–75CrossRef Baumgarten A, Tyagi A, Zambreno J (2010) Preventing ic piracy using reconfigurable logic barriers. IEEE Des Test Comput 27(1):66–75CrossRef
4.
go back to reference Bilzor M (2011) 3D execution monitor (3D-EM): using 3D circuits to detect hardware malicious inclusions in general purpose processors. In: Proceedings of the 6th international conference on information warfare and security, Academic Conferences Limited, p 288 Bilzor M (2011) 3D execution monitor (3D-EM): using 3D circuits to detect hardware malicious inclusions in general purpose processors. In: Proceedings of the 6th international conference on information warfare and security, Academic Conferences Limited, p 288
5.
go back to reference Bobba S, Chakraborty A, Thomas O, Batude P, Pavlidis VF, De Micheli G (2010) Performance analysis of 3-D monolithic integrated circuits. In: IEEE international 3D systems integration conference (3DIC), 2010, IEEE, pp 1–4 Bobba S, Chakraborty A, Thomas O, Batude P, Pavlidis VF, De Micheli G (2010) Performance analysis of 3-D monolithic integrated circuits. In: IEEE international 3D systems integration conference (3DIC), 2010, IEEE, pp 1–4
6.
go back to reference Chang YC, Chang YW, Wu GM, Wu SW (2000) B*-trees: a new representation for non-slicing floorplans. In: Proceedings of the 37th annual design automation conference, ACM, pp 458–463 Chang YC, Chang YW, Wu GM, Wu SW (2000) B*-trees: a new representation for non-slicing floorplans. In: Proceedings of the 37th annual design automation conference, ACM, pp 458–463
7.
go back to reference Chi CC, Marinissen EJ, Goel SK, Wu CW (2011) Post-bond testing of 2.5 d-sics and 3d-sics containing a passive silicon interposer base. In: IEEE international test conference (ITC), 2011, IEEE, pp 1–10 Chi CC, Marinissen EJ, Goel SK, Wu CW (2011) Post-bond testing of 2.5 d-sics and 3d-sics containing a passive silicon interposer base. In: IEEE international test conference (ITC), 2011, IEEE, pp 1–10
8.
go back to reference Contreras GK, Rahman MT, Tehranipoor M (2013) Secure split-test for preventing IC piracy by untrusted foundry and assembly. In: IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFT), 2013, IEEE, pp 196–203 Contreras GK, Rahman MT, Tehranipoor M (2013) Secure split-test for preventing IC piracy by untrusted foundry and assembly. In: IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFT), 2013, IEEE, pp 196–203
9.
go back to reference Fiduccia CM, Mattheyses RM (1982) A linear-time heuristic for improving network partitions. In: 19th conference on design automation, 1982, IEEE, pp 175–181 Fiduccia CM, Mattheyses RM (1982) A linear-time heuristic for improving network partitions. In: 19th conference on design automation, 1982, IEEE, pp 175–181
10.
go back to reference Garrou P, Bower C, Ramm P (2011) Handbook of 3d integration: volume 1-technology and applications of 3D integrated circuits. Wiley, New York Garrou P, Bower C, Ramm P (2011) Handbook of 3d integration: volume 1-technology and applications of 3D integrated circuits. Wiley, New York
12.
go back to reference Guin U, Huang K, DiMase D, Carulli JM, Tehranipoor M, Makris Y (2014) Counterfeit integrated circuits: a rising threat in the global semiconductor supply chain. Proc IEEE 102(8):1207–1228CrossRef Guin U, Huang K, DiMase D, Carulli JM, Tehranipoor M, Makris Y (2014) Counterfeit integrated circuits: a rising threat in the global semiconductor supply chain. Proc IEEE 102(8):1207–1228CrossRef
13.
go back to reference Ho YK, Chang YW (2013) Multiple chip planning for chip-interposer codesign. In: 2013 50th ACM/EDAC/IEEE design automation conference (DAC), IEEE, pp 1–6 Ho YK, Chang YW (2013) Multiple chip planning for chip-interposer codesign. In: 2013 50th ACM/EDAC/IEEE design automation conference (DAC), IEEE, pp 1–6
14.
go back to reference Hsieh AC, Hwang T (2012) TSV redundancy: architecture and design issues in 3-D IC. IEEE Trans Very Large Scale Integr (VLSI) Sys 20(4):711–722 Hsieh AC, Hwang T (2012) TSV redundancy: architecture and design issues in 3-D IC. IEEE Trans Very Large Scale Integr (VLSI) Sys 20(4):711–722
15.
go back to reference Imeson F, Emtenan A, Garg S, Tripunitara M (2013) Securing computer hardware using 3d integrated circuit (IC) technology and split manufacturing for obfuscation. In: Presented as part of the 22nd USENIX security symposium (USENIX Security 13), pp 495–510 Imeson F, Emtenan A, Garg S, Tripunitara M (2013) Securing computer hardware using 3d integrated circuit (IC) technology and split manufacturing for obfuscation. In: Presented as part of the 22nd USENIX security symposium (USENIX Security 13), pp 495–510
16.
go back to reference Jagasivamani M, Gadfort P, Sika M, Bajura M, Fritze M (2014) Split-fabrication obfuscation: metrics and techniques. In: IEEE international symposium on hardware-oriented security and trust (HOST), 2014, IEEE, pp 7–12 Jagasivamani M, Gadfort P, Sika M, Bajura M, Fritze M (2014) Split-fabrication obfuscation: metrics and techniques. In: IEEE international symposium on hardware-oriented security and trust (HOST), 2014, IEEE, pp 7–12
17.
go back to reference Jung M, Song T, Wan Y, Peng Y, Lim SK (2014) On enhancing power benefits in 3d ICs: block folding and bonding styles perspective. In: Proceedings of the 51st annual design automation conference, ACM, pp 1–6 Jung M, Song T, Wan Y, Peng Y, Lim SK (2014) On enhancing power benefits in 3d ICs: block folding and bonding styles perspective. In: Proceedings of the 51st annual design automation conference, ACM, pp 1–6
18.
go back to reference Khaleghi S, Da Zhao K, Rao W (2015) IC piracy prevention via design withholding and entanglement. In: The 20th Asia and south Pacific design automation conference, IEEE, pp 821–826 Khaleghi S, Da Zhao K, Rao W (2015) IC piracy prevention via design withholding and entanglement. In: The 20th Asia and south Pacific design automation conference, IEEE, pp 821–826
19.
go back to reference Li J, Lach J, (2008) At-speed delay characterization for IC authentication and trojan horse detection. In: IEEE international workshop on hardware-oriented security and trust (HOST), 2008, IEEE, pp 8–14 Li J, Lach J, (2008) At-speed delay characterization for IC authentication and trojan horse detection. In: IEEE international workshop on hardware-oriented security and trust (HOST), 2008, IEEE, pp 8–14
20.
go back to reference Liu B, Qu G (2016) VLSI supply chain security risks and mitigation techniques: a survey. Integr. VLSI J 55:438–448 Liu B, Qu G (2016) VLSI supply chain security risks and mitigation techniques: a survey. Integr. VLSI J 55:438–448
21.
go back to reference Liu B, Wang B (2014) Embedded reconfigurable logic for asic design obfuscation against supply chain attacks. In: Proceedings of the conference on design, automation & test in Europe, European Design and Automation Association, p 243 Liu B, Wang B (2014) Embedded reconfigurable logic for asic design obfuscation against supply chain attacks. In: Proceedings of the conference on design, automation & test in Europe, European Design and Automation Association, p 243
22.
go back to reference Loh GH, Xie Y, Black B (2007) Processor design in 3d die-stacking technologies. IEEE Micro 27(3):31–48CrossRef Loh GH, Xie Y, Black B (2007) Processor design in 3d die-stacking technologies. IEEE Micro 27(3):31–48CrossRef
23.
go back to reference Lu T, Srivastava A (2015) Electromigration-aware clock tree synthesis for tsv-based 3d-ics. In: Proceedings of the 25th edition on Great Lakes symposium on VLSI, ACM, pp 27–32 Lu T, Srivastava A (2015) Electromigration-aware clock tree synthesis for tsv-based 3d-ics. In: Proceedings of the 25th edition on Great Lakes symposium on VLSI, ACM, pp 27–32
24.
go back to reference Marinissen EJ (2012) Challenges and emerging solutions in testing TSV-based 2 1/2D-and 3D-stacked ICs. In: Proceedings of the conference on design, automation and test in Europe, EDA Consortium, pp 1277–1282 Marinissen EJ (2012) Challenges and emerging solutions in testing TSV-based 2 1/2D-and 3D-stacked ICs. In: Proceedings of the conference on design, automation and test in Europe, EDA Consortium, pp 1277–1282
25.
go back to reference Marinissen EJ, De Wachter B, O’Loughlin S, Deutsch S, Papameletis C, Burgherr T (2014) Vesuvius-3D: a 3D-DfT demonstrator. In: IEEE international test conference (ITC), 2014, IEEE, pp 1–10 Marinissen EJ, De Wachter B, O’Loughlin S, Deutsch S, Papameletis C, Burgherr T (2014) Vesuvius-3D: a 3D-DfT demonstrator. In: IEEE international test conference (ITC), 2014, IEEE, pp 1–10
26.
go back to reference Narasimhan S, Yueh W, Wang X, Mukhopadhyay S, Bhunia S (2012) Improving IC security against trojan attacks through integration of security monitors. IEEE Des Test Comput 29(5):37–46CrossRef Narasimhan S, Yueh W, Wang X, Mukhopadhyay S, Bhunia S (2012) Improving IC security against trojan attacks through integration of security monitors. IEEE Des Test Comput 29(5):37–46CrossRef
27.
go back to reference Plaza SM, Markov IL (2015) Solving the third-shift problem in ic piracy with test-aware logic locking. IEEE Trans Comput-Aided Des Integr Circuits Syst 34(6):961–971CrossRef Plaza SM, Markov IL (2015) Solving the third-shift problem in ic piracy with test-aware logic locking. IEEE Trans Comput-Aided Des Integr Circuits Syst 34(6):961–971CrossRef
28.
go back to reference Rajendran J, Pino Y, Sinanoglu O, Karri R (2012) Security analysis of logic obfuscation. In: Proceedings of the 49th annual design automation conference, ACM, pp 83–89 Rajendran J, Pino Y, Sinanoglu O, Karri R (2012) Security analysis of logic obfuscation. In: Proceedings of the 49th annual design automation conference, ACM, pp 83–89
29.
go back to reference Rajendran J, Sinanoglu O, Karri R (2013) Is split manufacturing secure? In: Design, automation & test in Europe conference & exhibition (DATE), 2013, IEEE, pp 1259–1264 Rajendran J, Sinanoglu O, Karri R (2013) Is split manufacturing secure? In: Design, automation & test in Europe conference & exhibition (DATE), 2013, IEEE, pp 1259–1264
30.
go back to reference Rajendran J, Sinanoglu O, Karri R (2014) Regaining trust in VLSI design: design-for-trust techniques. Proc IEEE 102(8):1266–1282CrossRef Rajendran J, Sinanoglu O, Karri R (2014) Regaining trust in VLSI design: design-for-trust techniques. Proc IEEE 102(8):1266–1282CrossRef
31.
go back to reference Rajendran J, Zhang H, Zhang C, Rose GS, Pino Y, Sinanoglu O, Karri R (2015) Fault analysis-based logic encryption. IEEE Trans Comput 64(2):410–424MathSciNetCrossRef Rajendran J, Zhang H, Zhang C, Rose GS, Pino Y, Sinanoglu O, Karri R (2015) Fault analysis-based logic encryption. IEEE Trans Comput 64(2):410–424MathSciNetCrossRef
32.
go back to reference Rostami M, Koushanfar F, Rajendran J, Karri R (2013) Hardware security: threat models and metrics. In: Proceedings of the international conference on computer-aided design, IEEE Press, pp 819–823 Rostami M, Koushanfar F, Rajendran J, Karri R (2013) Hardware security: threat models and metrics. In: Proceedings of the international conference on computer-aided design, IEEE Press, pp 819–823
33.
go back to reference Roy JA, Koushanfar F, Markov IL (2008) Epic: ending piracy of integrated circuits. In: Proceedings of the conference on design, automation and test in Europe, ACM, pp 1069–1074 Roy JA, Koushanfar F, Markov IL (2008) Epic: ending piracy of integrated circuits. In: Proceedings of the conference on design, automation and test in Europe, ACM, pp 1069–1074
34.
go back to reference Saban K (2011) Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. Xilinx, White Paper Saban K (2011) Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. Xilinx, White Paper
35.
go back to reference Salmani H, Tehranipoor M, Plusquellic J, (2009) New design strategy for improving hardware trojan detection and reducing trojan activation time. In: IEEE international workshop on hardware-oriented security and trust (HOST’09), 2009, IEEE, pp 66–73 Salmani H, Tehranipoor M, Plusquellic J, (2009) New design strategy for improving hardware trojan detection and reducing trojan activation time. In: IEEE international workshop on hardware-oriented security and trust (HOST’09), 2009, IEEE, pp 66–73
36.
go back to reference Subramanyan P, Ray S, Malik S (2015) Evaluating the security of logic encryption algorithms. In: IEEE international symposium on hardware oriented security and trust (HOST), 2015, IEEE, pp 137–143 Subramanyan P, Ray S, Malik S (2015) Evaluating the security of logic encryption algorithms. In: IEEE international symposium on hardware oriented security and trust (HOST), 2015, IEEE, pp 137–143
37.
go back to reference Taouil M, Hamdioui S, Beenakker K, Marinissen EJ (2010) Test cost analysis for 3D die-to-wafer stacking. In: 19th IEEE asian test symposium (ATS), 2010, IEEE, pp 435–441 Taouil M, Hamdioui S, Beenakker K, Marinissen EJ (2010) Test cost analysis for 3D die-to-wafer stacking. In: 19th IEEE asian test symposium (ATS), 2010, IEEE, pp 435–441
39.
go back to reference Torrance R, James D (2009) The state-of-the-art in IC reverse engineering. In: Cryptographic hardware and embedded systems-CHES 2009, Springer, Berlin, pp 363–381 Torrance R, James D (2009) The state-of-the-art in IC reverse engineering. In: Cryptographic hardware and embedded systems-CHES 2009, Springer, Berlin, pp 363–381
40.
go back to reference Vaidyanathan K, Das BP, Sumbul E, Liu R, Pileggi L (2014) Building trusted ics using split fabrication. In: IEEE international symposium on hardware-oriented security and trust (HOST), 2014, IEEE, pp 1–6 Vaidyanathan K, Das BP, Sumbul E, Liu R, Pileggi L (2014) Building trusted ics using split fabrication. In: IEEE international symposium on hardware-oriented security and trust (HOST), 2014, IEEE, pp 1–6
41.
go back to reference Vaidyanathan K, Liu R, Sumbul E, Zhu Q, Franchetti F, Pileggi L (2014) Efficient and secure intellectual property (IP) design with split fabrication. In: IEEE international symposium on hardware-oriented security and trust (HOST), 2014, IEEE, pp 13–18 Vaidyanathan K, Liu R, Sumbul E, Zhu Q, Franchetti F, Pileggi L (2014) Efficient and secure intellectual property (IP) design with split fabrication. In: IEEE international symposium on hardware-oriented security and trust (HOST), 2014, IEEE, pp 13–18
42.
go back to reference Valamehr J, Sherwood T, Kastner R, Marangoni-Simonsen D, Huffmire T, Irvine C, Levin T (2013) A 3-D split manufacturing approach to trustworthy system development. IEEE Trans Comput-Aided Des Integr Circuits Syst 32(4):611–615 Valamehr J, Sherwood T, Kastner R, Marangoni-Simonsen D, Huffmire T, Irvine C, Levin T (2013) A 3-D split manufacturing approach to trustworthy system development. IEEE Trans Comput-Aided Des Integr Circuits Syst 32(4):611–615
43.
go back to reference Wendt JB, Potkonjak M (2014) Hardware obfuscation using puf-based logic. In: Proceedings of the 2014 IEEE/ACM international conference on computer-aided design, IEEE Press, pp 270–277 Wendt JB, Potkonjak M (2014) Hardware obfuscation using puf-based logic. In: Proceedings of the 2014 IEEE/ACM international conference on computer-aided design, IEEE Press, pp 270–277
44.
go back to reference Xiao K, Tehranipoor M (2013) BISA: Built-in self-authentication for preventing hardware trojan insertion. In: IEEE international symposium on hardware-oriented security and trust (HOST), 2013, IEEE, pp 45–50 Xiao K, Tehranipoor M (2013) BISA: Built-in self-authentication for preventing hardware trojan insertion. In: IEEE international symposium on hardware-oriented security and trust (HOST), 2013, IEEE, pp 45–50
45.
go back to reference Xiao K, Forte D, Tehranipoor MM (2015) Efficient and secure split manufacturing via obfuscated built-in self-authentication. In: IEEE international symposium on hardware oriented security and trust (HOST), 2015, IEEE, pp 14–19 Xiao K, Forte D, Tehranipoor MM (2015) Efficient and secure split manufacturing via obfuscated built-in self-authentication. In: IEEE international symposium on hardware oriented security and trust (HOST), 2015, IEEE, pp 14–19
46.
go back to reference Xie Y, Bao C, Serafy C, Lu T, Srivastava A, Tehranipoor M (2015) Security and vulnerability implications of 3d ics. IEEE Trans Multi-Scale Comput Syst 2(2):108–122CrossRef Xie Y, Bao C, Serafy C, Lu T, Srivastava A, Tehranipoor M (2015) Security and vulnerability implications of 3d ics. IEEE Trans Multi-Scale Comput Syst 2(2):108–122CrossRef
47.
go back to reference Xie Y, Bao C, Srivastava A (2015) Security-aware design flow for 2.5 d ic technology. In: Proceedings of the 5th international workshop on trustworthy embedded devices, ACM, pp 31–38 Xie Y, Bao C, Srivastava A (2015) Security-aware design flow for 2.5 d ic technology. In: Proceedings of the 5th international workshop on trustworthy embedded devices, ACM, pp 31–38
48.
go back to reference Yasin M, Saeed SM, Rajendran J, Sinanoglu O (2016) Activation of logic encrypted chips: Pre-test or post-test? In: 2016 design, automation & test in Europe conference & exhibition (DATE), IEEE, pp 139–144 Yasin M, Saeed SM, Rajendran J, Sinanoglu O (2016) Activation of logic encrypted chips: Pre-test or post-test? In: 2016 design, automation & test in Europe conference & exhibition (DATE), IEEE, pp 139–144
Metadata
Title
3D/2.5D IC-Based Obfuscation
Authors
Yang Xie
Chongxi Bao
Ankur Srivastava
Copyright Year
2017
DOI
https://doi.org/10.1007/978-3-319-49019-9_12