A degradable NoC router for the improvement of fault-tolerant routing performance

Network-on-chip (NoC) provides high computation performance for a wide range of applications including robotics and artificial intelligence. This paper deals with the issue of improving the fault-tolerant routing performance for realizing high-performance NoCs. The major drawbacks of the conventional fault-tolerant routing methods are low node utilization efficacy and high communication latency. To solve these problems, we propose a novel NoC router which enables to logically reconstruct faulty input buffers. In contrast to most conventional methods, where routers with partially faulty input buffers are regarded as faulty, the proposed method regards them as fault-free routers with degraded input buffers. Simulation results obtained by a cycle accurate custom simulator show that the proposed method reduces the number of faulty and unused nodes and improves communication latency by up to 93% and 87%, respectively, compared with the conventional methods.