An Advanced Encryption Standard in Memory (AESIM) Efficient, High Performance S-box Based AES Encryption and Decryption Architecture on VLSI

As CMOS(Complementary Metal Oxide Semiconductor) technology reaches its scaling threshold, evolving non-volatile memory approaches are becoming a hopeful substitutes to Dynamic RAM (i.e.) DRAM because of the low leakage power and improved scalability. Nonetheless, a new security flaw concerns the non-volatile central memory system. An intruder can easily access confidential memory records, as the non-volatility cause’s knowledge to be stored even after the electricity is off for a long time. While memory encryption in real-time is an efficient way for dealing with this vulnerability in memory accesses along with an exclusive Advanced Encryption Standard (AES) engine, runtime performance and overhead energy are involved. The proposed work is to combine the AES key and the ECC key alternately for encryption and decryption and hence, a quick and efficient application of AES in memory (AESIM) was proposed in the paper to encrypt the either a part of the memory or the entire only if it is needed. Instead of counting additional processing elements to the cost-sensitive memory, the intrinsic logic operating capability of NVM was utilized to employ the proposed AESIM technique. We take advantage of the assistances provided by the in-memory storage design (huge internal bandwidth and dramatic reduction in movement of data) to overcome the complexities of the bandwidth concentrated encryption method. S-box is utilized along with AESIM methodology for performing the encryption process and then the counter action of decryption is performed by the inverse S-box which is employed with the AESIM. By embracing the memory's massive parallelism, AESIM outperforms current methods with higher performance yet lower consumption of energy. The efficiency of the proposed AESIM technique is calculated for both encryption and decryption process by measuring the minimum time used, the minimum time taken for the time before clock delivery, the average time required for operation after clock, the latency and the amount of logic separately for the proposed AESIM encryption and decryption technique.