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Published in: Journal of Electronic Testing 2/2016

11-03-2016

Applications of Mixed-Signal Technology in Digital Testing

Authors: Baohu Li, Vishwani D. Agrawal

Published in: Journal of Electronic Testing | Issue 2/2016

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Abstract

For reducing the test application time and required tester pins per device, we propose the use of multi-valued logic (MVL) signals, which increases data rate between the device under test (DUT) and automatic test equipment (ATE). An MVL signal sends multiple bits of information per clock cycle on a physical channel. Conversion of signals between binary and MVL is accomplished by digital to analog and analog to digital converters available in the mixed-signal technology. To support MVL test application and avoid reliability issues, we add necessary modifications on ATE and DUT sides. Theoretical calculation and a prototype experiment demonstrate significant data rate increase. We integrate the proposed MVL technique into test methodologies involving reduced pin-count test (RPCT) for multi-core system-on-chip (SoC) and test compression. An actual automatic test equipment (ATE) based test of a DUT shows notable reduction in test application time with MVL test application.

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Literature
3.
go back to reference Advantest R&D Center Inc. OPENSTAR Test Programming Language (OTPL) (2003) Advantest Corporation technical publication Advantest R&D Center Inc. OPENSTAR Test Programming Language (OTPL) (2003) Advantest Corporation technical publication
5.
go back to reference Basu K, Mishra P (2010) Test data compression using efficient bitmask and dictionary selection methods. IEEE Trans Very Large Scale Integration Syst 18(9):1277–1286CrossRef Basu K, Mishra P (2010) Test data compression using efficient bitmask and dictionary selection methods. IEEE Trans Very Large Scale Integration Syst 18(9):1277–1286CrossRef
6.
go back to reference Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Springer Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Springer
8.
go back to reference Chakravadhanula K, Chickermane V, Pearl D, Garg A, Khurana R, Mukherjee S, Nagaraj P (2013) SmartScan - hierarchical test compression for pin-limited low power designs. In: Proceedings of IEEE international test conference. Paper 4.2 Chakravadhanula K, Chickermane V, Pearl D, Garg A, Khurana R, Mukherjee S, Nagaraj P (2013) SmartScan - hierarchical test compression for pin-limited low power designs. In: Proceedings of IEEE international test conference. Paper 4.2
9.
go back to reference Chandra A, Kapur R, Kanzawa Y (2009) Scalable Adaptive Scan (SAS). In: Proceedings of design, automation and test in Europe conference and exhibition, pp 1476–1481 Chandra A, Kapur R, Kanzawa Y (2009) Scalable Adaptive Scan (SAS). In: Proceedings of design, automation and test in Europe conference and exhibition, pp 1476–1481
10.
go back to reference Chillarige S, Virdi S, Malik A, Chakravadhanula K, Chickermane V, Swenton J, Vandling G (2015) A novel failure diagnosis approach for low pin count and low power compression architectures. In: Proceedings of 24th IEEE North Atlantic test workshop, pp 43–48 Chillarige S, Virdi S, Malik A, Chakravadhanula K, Chickermane V, Swenton J, Vandling G (2015) A novel failure diagnosis approach for low pin count and low power compression architectures. In: Proceedings of 24th IEEE North Atlantic test workshop, pp 43–48
11.
go back to reference Greshishchev Y, Pollex D, Wang S-C, Besson M, Flemeke P, Szilagyi S, Aguirre J, Falt C, Ben-Hamida N, Gibbins R, Schvan P (2011) A 56GS/S 6b DAC in 65nm CMOS with 256x6b Memory. In: IEEE solid-state circuits conference digest of technical papers, pp 194–196 Greshishchev Y, Pollex D, Wang S-C, Besson M, Flemeke P, Szilagyi S, Aguirre J, Falt C, Ben-Hamida N, Gibbins R, Schvan P (2011) A 56GS/S 6b DAC in 65nm CMOS with 256x6b Memory. In: IEEE solid-state circuits conference digest of technical papers, pp 194–196
12.
go back to reference Gustavsson M, Wikner JJ, Tan NN (2000) CMOS data converters for communications. Springer Gustavsson M, Wikner JJ, Tan NN (2000) CMOS data converters for communications. Springer
13.
go back to reference Kavousianos X, Kalligeros E, Nikolos D (2007) Optimal selective Huffman coding for test-data compression. IEEE Trans Comput 56(8):1146–1152MathSciNetCrossRef Kavousianos X, Kalligeros E, Nikolos D (2007) Optimal selective Huffman coding for test-data compression. IEEE Trans Comput 56(8):1146–1152MathSciNetCrossRef
14.
go back to reference Koob JC, Ung SA, Cockburn BF, Elliott DG (2011) Design and characterization of a multilevel DRAM. IEEE Trans Very Large Scale Integration Syst 19(9):1583–1596CrossRef Koob JC, Ung SA, Cockburn BF, Elliott DG (2011) Design and characterization of a multilevel DRAM. IEEE Trans Very Large Scale Integration Syst 19(9):1583–1596CrossRef
15.
go back to reference Kull L, Toifl T, Schmatz M, Francese P, Menolfi C, Braendli M, Kossel M, Morf T, Andersen T, Leblebici Y (2014) A 90GS/s 8b 667mW 64 interleaved SAR ADC in 32nm Digital SOI CMOS. In: IEEE international solid-state circuits conference digest of technical papers, pp 378–379 Kull L, Toifl T, Schmatz M, Francese P, Menolfi C, Braendli M, Kossel M, Morf T, Andersen T, Leblebici Y (2014) A 90GS/s 8b 667mW 64 interleaved SAR ADC in 32nm Digital SOI CMOS. In: IEEE international solid-state circuits conference digest of technical papers, pp 378–379
17.
go back to reference Li B. (2015) Digital testing with multi-valued logic signals. PhD thesis, Auburn University, Alabama Li B. (2015) Digital testing with multi-valued logic signals. PhD thesis, Auburn University, Alabama
18.
go back to reference Li B, Agrawal VD (2015) Multivalued logic for reduced pin count and multi-site SoC testing. In: Proceedings of 24th IEEE North Atlantic test workshop, pp 49–54 Li B, Agrawal VD (2015) Multivalued logic for reduced pin count and multi-site SoC testing. In: Proceedings of 24th IEEE North Atlantic test workshop, pp 49–54
20.
go back to reference Li B, Zhang B, Agrawal VD (2015) Adopting multi-valued logic for reduced pin-count testing. In: Proceedings of 16th Latin-American test symposium Li B, Zhang B, Agrawal VD (2015) Adopting multi-valued logic for reduced pin-count testing. In: Proceedings of 16th Latin-American test symposium
21.
go back to reference Li L, Chakrabarty K (2003) Test data compression using dictionaries with fixed-length indices. In: Proceedings of 21st IEEE VLSI test symposium, pp 219–224 Li L, Chakrabarty K (2003) Test data compression using dictionaries with fixed-length indices. In: Proceedings of 21st IEEE VLSI test symposium, pp 219–224
22.
go back to reference Li T, Ni Q, Malone D, Leith D, Xiao Y, Turletti T (2009) Aggregation with fragment retransmission for very high-speed WLANs. IEEE/ACM Trans Netw 17(2):591–604CrossRef Li T, Ni Q, Malone D, Leith D, Xiao Y, Turletti T (2009) Aggregation with fragment retransmission for very high-speed WLANs. IEEE/ACM Trans Netw 17(2):591–604CrossRef
23.
go back to reference Lin C-H, Bult K. (Dec. 1998) A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2. IEEE J Solid State Circuits 33(12):1948–1958 Lin C-H, Bult K. (Dec. 1998) A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2. IEEE J Solid State Circuits 33(12):1948–1958
25.
go back to reference Mochizuki A, Hanyu T (2005) A 1.88ns 54×54-bit multiplier in 0.18μm CMOS based on multiple-valued differential-pair circuitry. In: Symposium on VLSI circuits digest of technical papers, pp 264–267 Mochizuki A, Hanyu T (2005) A 1.88ns 54×54-bit multiplier in 0.18μm CMOS based on multiple-valued differential-pair circuitry. In: Symposium on VLSI circuits digest of technical papers, pp 264–267
26.
go back to reference Moreau J, Droniou T, Lebourg P, Armagnat P (2009) Running scan test on three pins: yes we can!. In: Proceedings of IEEE international test conference. Paper 18.1 Moreau J, Droniou T, Lebourg P, Armagnat P (2009) Running scan test on three pins: yes we can!. In: Proceedings of IEEE international test conference. Paper 18.1
27.
go back to reference Murmann B (2013) A/D converter circuit and architecture design for high-speed data communication. In: Proceedings of custom integrated circuits conference, pp 1–78 Murmann B (2013) A/D converter circuit and architecture design for high-speed data communication. In: Proceedings of custom integrated circuits conference, pp 1–78
29.
go back to reference Nakajima T, Yaguchi T, Sugimura H (2012) An ATE architecture for implementing very high efficiency concurrent testing. In: Proceedings of IEEE international test conference. Paper7.1 Nakajima T, Yaguchi T, Sugimura H (2012) An ATE architecture for implementing very high efficiency concurrent testing. In: Proceedings of IEEE international test conference. Paper7.1
32.
go back to reference Rajski J, Tyszer J, Kassab M, Mukherjee N (May 2004) Embedded deterministic test. IEEE Trans Comput Aided Des Integr Circuits Syst 23(5):776–792 Rajski J, Tyszer J, Kassab M, Mukherjee N (May 2004) Embedded deterministic test. IEEE Trans Comput Aided Des Integr Circuits Syst 23(5):776–792
33.
go back to reference Sanghani A, Yang B, Natarajan K, Liu C (2011) Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. In: Proceedings of 29th IEEE VLSI test symposium, pp 219–224 Sanghani A, Yang B, Natarajan K, Liu C (2011) Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. In: Proceedings of 29th IEEE VLSI test symposium, pp 219–224
34.
go back to reference Song B, Kim K, Lee J, Burm J (Feb. 2013) A 0.18- μm CMOS 10-Gb/s Dual-Mode 10-PAM serial link transceiver. IEEE Trans Circuits Syst 60(2):457–468 Song B, Kim K, Lee J, Burm J (Feb. 2013) A 0.18- μm CMOS 10-Gb/s Dual-Mode 10-PAM serial link transceiver. IEEE Trans Circuits Syst 60(2):457–468
36.
go back to reference Takahashi Y, Maeda A (2011) Multi domain test: novel test strategy to reduce the cost of test. In: Proceedings of 29th IEEE VLSI test symposium, pp 303–308 Takahashi Y, Maeda A (2011) Multi domain test: novel test strategy to reduce the cost of test. In: Proceedings of 29th IEEE VLSI test symposium, pp 303–308
37.
go back to reference Tehranipoor M, Nourani M, Arabi K, Afzali-Kusha A (2004) Mixed RL-huffman encoding for power reduction and data compression in scan test. In: Proceedings of international symposium circuits and systems, vol 2, pp 681–684 Tehranipoor M, Nourani M, Arabi K, Afzali-Kusha A (2004) Mixed RL-huffman encoding for power reduction and data compression in scan test. In: Proceedings of international symposium circuits and systems, vol 2, pp 681–684
39.
go back to reference Touba NA (2006) Survey of test vector compression techniques. IEEE Des Test Comput 23(4):294–303CrossRef Touba NA (2006) Survey of test vector compression techniques. IEEE Des Test Comput 23(4):294–303CrossRef
40.
go back to reference Volkerink E, Khoche A, Kamas L, Rivoir J, Kerkhoff H (2001) Tackling test trade-offs from design, manufacturing to market using economic modeling. In: Proceedings of IEEE international test conference, pp 1098–1107 Volkerink E, Khoche A, Kamas L, Rivoir J, Kerkhoff H (2001) Tackling test trade-offs from design, manufacturing to market using economic modeling. In: Proceedings of IEEE international test conference, pp 1098–1107
41.
go back to reference Vranken G, Waayers T, Fleury H, Lelouvier D (2001) Enhanced reduced pin-count test for full-scan design. In: Proceedings of IEEE international test conference, pp 738–747 Vranken G, Waayers T, Fleury H, Lelouvier D (2001) Enhanced reduced pin-count test for full-scan design. In: Proceedings of IEEE international test conference, pp 738–747
42.
go back to reference Volkerink E, Khoche A, Rivoir J, Hilliges K (2002) Test economics for multi-site test with modern cost reduction techniques. In: Proceedings of 20th IEEE VLSI test symposium, pp 411–416 Volkerink E, Khoche A, Rivoir J, Hilliges K (2002) Test economics for multi-site test with modern cost reduction techniques. In: Proceedings of 20th IEEE VLSI test symposium, pp 411–416
44.
go back to reference Wang L-T, Wu C-W, Wen X (2006) VLSI test principles and architectures. Morgan Kaufmann Wang L-T, Wu C-W, Wen X (2006) VLSI test principles and architectures. Morgan Kaufmann
Metadata
Title
Applications of Mixed-Signal Technology in Digital Testing
Authors
Baohu Li
Vishwani D. Agrawal
Publication date
11-03-2016
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 2/2016
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-016-5576-2

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