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International Journal of Speech Technology

Published in:

10-02-2020

ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems

Authors: Grande Naga Jyothi, Kishore Sanapala, A. Vijayalakshmi

Published in: International Journal of Speech Technology | Issue 2/2020

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Abstract

Digital signal processing (DSP) systems are becoming popular with the emergence of artificial intelligence and machine learning based applications. Residue number system is one of most sought representation for implementing the high speed DSP systems. This paper presents an efficient implementation of memory less distributed arithmetic (MLDA) architecture in finite impulse response filter with residual number system. The input data and filter coefficients of MLDA are in residue number form and the output data from MLDA is converted into binary form using Chinese remainder theorem. In addition, compressor adders are used to reduce the area. For real time validation, the proposed design has been simulated and synthesized in application specific integrated circuit platform using synopsis design compiler with CMOS 90 nm technology. The results show that the proposed design has very high computation speed with total delay of only 20 ns and occupies 20% less area in comparison with the existing designs.

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Bernocchi, G. L., et al. (2006). A hybrid RNS adaptive filter for channel equalization. In IEEE fortieth asilomar conference on signals, systems and computers.

Cao, B., Chang, C.-H., & Srikanthan, T. (2003). An efficient reverse converter for the 4-moduli set 2^n–1, 2ⁿ, 2ⁿ⁺¹, 2²ⁿ⁺¹ based on the new Chinese remainder theorem. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications,50(10), 1296–1303.MathSciNetCrossRef

Chang, C. H., et al. (2015). Residue number systems: A new paradigm to datapath optimization for low-power and high-performance digital signal processing applications. IEEE Circuits and Systems Magazine,15(4), 26–44.CrossRef

Chen, K.-H., & Chiueh, T.-D. (2006). A low-power digit-based reconfigurable FIR filter. IEEE Transactions on Circuits and Systems II,53(8), 617–621.CrossRef

Fayed, A., & Bayoumi, M. A. (2002). A merged multiplier accumulator for high speed signal processing applications. In 2002 IEEE international conference on acoustics, speech, and signal processing.

Ghamkhari, S. F., & Ghaznavi-Ghoushchi, M. B. (2012). In 20th Iranian conference on electrical engineering (ICEE2012)

Hartley, R. (1996). Subexpression sharing in filters using canonic signed digit multipliers. IEEE Transactions on Circuits and Systems II,43(10), 677–688.CrossRef

Kamal, R., Chandravanshi, P., & Jain, N. (2014). Efficient VLSI architecture for FIR filter using DA-RNS. In IEEE international conference on electronics, communication and computational engineering (ICECCE).

Khoo, K.-Y., et al. (1996). A programmable FIR digital filter using CSD coefficients. IEEE Journal of Solid-State Circuits,3(1), 869–874.MathSciNetCrossRef

Kucherov, N. N., et al. (2018). A high-speed residue-to-binary converter based on approximate Chinese Remainder Theorem. In IEEE conference of Russian young researchers in electrical and electronic engineering (EIConRus).

Matutino, P. M., Chaves, R., & Sousa, L. (2014). ROM-less RNS-to-binary converter moduli 2^2n-1, 2²ⁿ⁺¹, 2^n-3, 2ⁿ⁺³. In IEEE 14th international symposium on integrated circuits (ISIC).

Matutino, P. M., Chaves, R., & Sousa, L. (2015). Arithmetic-based binary-to-RNS converter modulo 2n±k for JN-bit dynamic range. IEEE Transactions on VLSI System,23(3), 603–607.CrossRef

Meher, P. K., Chandrasekaran, S., & Amira, A. (2008). FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Transactions on Signal Processing,56(7), 3009–3017.MathSciNetCrossRef

Menon, S., & Chang, C.-H. (2006). A reconfigurable multi-modulus modulo multiplier. In IEEE Asia Pacific conference on circuits and systems.

Meyer-Base, U., García, A., & Taylor, F. (2001). Implementation of a communications channelizer using FPGAs and RNS arithmetic. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology,28(1), 115–128.CrossRef

Mohanty, B. K., & Meher, P. K. (2016). A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm. IEEE Transaction on Very Large Scale Integration Systems, 24(5)

Naga Jyothi, G., & Sri Devi, S. (2017). Distributed arithmetic architectures for FIR filters: A comparative review. IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET).

Naga Jyothi, G., & Sridevi, S. (2019). High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter. Multimedia Tools and Applications,78(23), 32679–32693.CrossRef

Parhi, K. (2007). VLSI digital signal processing systems: Design and implementation. New Delhi: Wiley.

Petrousov, G., & Dasygenis, M. (2014). A unique network EDA tool to create optimized ad hoc binary to residue number system converters. IEEE 24th international workshop on power and timing modeling, optimization and simulation (PATMOS).

Proakis, J. G. (2001). Digital signal processing: Principles algorithms and applications. New Delhi: Pearson Education India.

Rahul Narasimhan, A. (2015). High speed multiply-accumulator coprocessor realized for digital filters. IEEE international conference on electrical, computer and communication technologies (ICECCT).

Sanapala, K., Shree, L. R., & Sakthivel, R. (2018). Design of ultralow voltage-hybrid full adder circuit using GLBB scheme for energy-efficient arithmetic applications. In J. Anguera, S. Satapathy, V. Bhateja, & K. Sunitha (Eds.), Microelectronics, electromagnetics and telecommunications. Lecture notes in electrical engineering (pp. 217–223). Singapore: Springer.CrossRef

Shanthala, S., & Kulkarni, S. Y. (2009). VLSI design and implementation of low power MAC unit with block enabling technique. European Journal of Scientific Research,30(4), 620–630.

Vun, C. H., Premkumar, A. B., & Zhang, W. (2013). A new RNS based DA approach for inner product computation. IEEE Transactions on Circuits and Systems I,60(8), 2139–2152.MathSciNetCrossRef

Title: ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems
Authors: Grande Naga Jyothi
Kishore Sanapala
A. Vijayalakshmi
Publication date: 10-02-2020
Publisher: Springer US
Published in: International Journal of Speech Technology / Issue 2/2020
Print ISSN: 1381-2416
Electronic ISSN: 1572-8110
DOI: https://doi.org/10.1007/s10772-020-09683-1

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