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1992 | Book

Introduction Read chapter Read first chapter

Assessing Fault Model and Test Quality

Authors: Kenneth M. Butler, M. Ray Mercer

Publisher: Springer US

Book Series : The International Series in Engineering and Computer Science

Included in: Professional Book Archive

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About this book

For many years, the dominant fault model in automatic test pattern gen­ eration (ATPG) for digital integrated circuits has been the stuck-at fault model. The static nature of stuck-at fault testing when compared to the extremely dynamic nature of integrated circuit (IC) technology has caused many to question whether or not stuck-at fault based testing is still viable. Attempts at answering this question have not been wholly satisfying due to a lack of true quantification, statistical significance, and/or high computational expense. In this monograph we introduce a methodology to address the ques­ tion in a manner which circumvents the drawbacks of previous approaches. The method is based on symbolic Boolean functional analyses using Or­ dered Binary Decision Diagrams (OBDDs). OBDDs have been conjectured to be an attractive representation form for Boolean functions, although cases ex­ ist for which their complexity is guaranteed to grow exponentially with input cardinality. Classes of Boolean functions which exploit the efficiencies inherent in OBDDs to a very great extent are examined in Chapter 7. Exact equa­ tions giving their OBDD sizes are derived, whereas until very recently only size bounds have been available. These size equations suggest that straight­ forward applications of OBDDs to design and test related problems may not prove as fruitful as was once thought.

Table of Contents

Frontmatter
Chapter 1. Introduction
Abstract
The current level of complexity of integrated circuits (ICs) renders human-based test generation an extremely difficult if not impossible task. The job of test generation for mass produced ICs has thus been relegated to the domain of automated testing methods. Successful automatic test pattern generation (ATPG) requires the harmonious cooperation of two basic components: a model of physical failures called a fault model, and an algorithm capable of deriving tests for specific fault instances.
Kenneth M. Butler, M. Ray Mercer
Chapter 2. Fault Modeling
Abstract
Fault models for electronic circuits are abstractions of mechanisms which could cause the device of interest to fail. As we have seen, the quality of a test set is strongly correlated with the “quality” of the fault model used. In this chapter, we review the fundamentals of fault modeling for digital circuits and discuss the characteristics of the models used in this research.
Kenneth M. Butler, M. Ray Mercer
Chapter 3. Ordered Binary Decision Diagrams
Abstract
In order to facilitate a detailed study of the perturbations of various fault models on the normal functioning of a given circuit, it is helpful to have the capacity to find all the tests for each fault in a fault set. One procedure to gather this information would be to inject each fault in the fault set, one at a time, and simulate all possible input patterns, noting when departures from the good machine outputs occur for each fault. An exhaustive method similar to the one just described was proposed in [BEH82]. Obviously, the time required for exhaustive approaches can become prohibitive quickly as circuit sizes grow.
Kenneth M. Butler, M. Ray Mercer
Chapter 4. Automatic Test Pattern Generation
Abstract
One goal of this research has been to produce a viable measure of non-target defect coverage of test sets for target faults obtained from an ATPG system. Because many ATPG algorithms exist, each guided by different heuristics with varying behavior, it has been necessary to capture the essential components of these algorithms in a model of the process. This model will be discussed in detail in Chapter 11. In this section we concentrate on describing the common characteristics of conventional ATPG systems. The discussion will address solely techniques for test generation at the logic gate level.
Kenneth M. Butler, M. Ray Mercer
Chapter 5. Defect Level
Abstract
Consumers of large quantities of integrated circuits usually consider the reliability of the parts to be a major factor when selecting a manufacturer from whom they will purchase the devices they need. Specifically, if some consumer determines that the mass production of a system will require exactly 1000 copies of an IC, they obviously desire to be shipped at least 1000 functional chips. IC manufacturers generally protect themselves by shipping more parts than were ordered, knowing that since the production testing of the parts was not exhaustive, some parts may have been declared “good” when they were actually faulty. Because this issue of “quality level” is intimately tied to the level of testing to which the parts were subjected and the quality of the test itself, researchers have sought to more formally define quality level. The goals of this research are to study fault models and the quality of test sets that they provide. Thus, one possible benefit of this work is a more effective use of testing to screen out bad parts before they are shipped to the customer. It is therefore proper to review the more interesting developments in IC quality research.
Kenneth M. Butler, M. Ray Mercer
Chapter6. Test Performance Evaluation
Abstract
In order to better understand and continually improve the manufacturing test process, it would be helpful to have a definitive measure of the “quality” of the test sets used. One method of measuring test quality might be to simply monitor the field reject rate - the number of parts returned or reported to the manufacturer as faulty. However, this is a crude measure for several reasons. Circuits can be damaged by a number of post-manufacture phenomena such as electrostatic discharge effects, poor encapsulation or wire bonding, etc. Also, on very complex circuits, some faults may never be detected if the corresponding portion of circuitry is not used by the consumer.
Kenneth M. Butler, M. Ray Mercer
Chapter 7. OBDDs for Symmetric Functions
Abstract
Much of the analysis reported in this monograph has been achieved through the symbolic representation of Boolean functions. OBDDs have been conjectured to be an economical vehicle for Boolean functional manipulation, but just how efficient are they? There is no known canonical Boolean function representation which remains tractably bounded for any arbitrary switching function. However, the OBDD is linear in size for some functions which cannot be represented as compactly in other canonical forms. The exclusive-OR (XOR, ®) is an example of such a function. OBDD size has also been shown to grow exponentially for some functions regardless of the variable ordering. An example of this class of circuits is the integer multipler [BRYA91], although recent research has demonstrated techniques to address the problem [BURC91b].
Kenneth M. Butler, M. Ray Mercer
Chapter 8. Difference Propagation
Abstract
Topological circuit information can often be derived from algorithms with computational complexities linear in some size parameter such as gate count or input count. Functional information on the other hand, such as the syndrome (the proportion of ones in the Karnaugh map of the function, [SAVI80]) of a circuit line is often much more costly to obtain. While very fast fault simulators exist, e. g. [WAIC85], the sheer size of many circuits makes the exhaustive simulation of large fault sets impractical. As we saw in Section 4.3, the use of Boolean functional techniques, on the other hand, has shown promise for applications where a great deal of information is needed, such as redundancy proving [GAED88], [STAN88]. We have adopted a similar function-based approach in this research.
Kenneth M. Butler, M. Ray Mercer
Chapter 9. Fault Model Behavior
Abstract
One aspect of paramount importance in deterministic testing is the performance of the fault models underlying the process. Recent research has shown that the fabrication process of a circuit is certainly an issue when measuring fault model performance [SHEN85]. However, it is also useful and informative to consider the functional limitations of fault models relative to the circuits themselves and independently of the technology chosen to realize them. Exhaustive simulation or simulation of particular test sets is one possible method that can be used to attack this sort of problem [HUGH86], [MILL88], [MILL89]. However, this approach is limited to relatively small samples of test sets due to otherwise exorbitant computation time requirements.
Kenneth M. Butler, M. Ray Mercer
Chapter 10. The Contributions of Controllability and Observability to Test
Abstract
Structural testing is based on the notions of controllability and observability. Controllability generally refers to the application of circuit stimulus such that the presence of a fault will cause some site(s) in the circuit to be logically different than when the fault is absent. Observability concerns the causation of a condition whereby the difference at the site(s) would force a logical difference at some circuit output where it can be directly measured. These quantities will be more formally defined in a later section.
Kenneth M. Butler, M. Ray Mercer
Chapter 11. Analyzing Test Performance with the ATPG Model
Abstract
As we saw in the Introduction and again in Chapter 6, the quality of test sets is an important quantity, but one that is difficult to define and measure. Even if a suitable metric is defined, most existing methods to quantify the metrics fail to provide an acceptable level of statistical significance. In contrast, our method examines the properties of the entire set of one-vector-per-fault test sets. This number can be quite large.
Kenneth M. Butler, M. Ray Mercer
Chapter 12. Conclusions
Abstract
The rapid advance of integrated circuit technology has made possible the fabrication of devices containing literally millions of devices. The associated problem of testing such complicated circuits and correctly certifying as “good” only those which are truly fault free has thus been compounded. In this environment, testing costs are now a significant proportion of the costs of fabricating ICs. The economics of this situation places a high priority on obtaining the highest performance possible out of automated test methods.
Kenneth M. Butler, M. Ray Mercer
Chapter 13. Suggestions for Future Research
Abstract
In the course of these investigations, many interesting questions have arisen that, due to time considerations, will remain unanswered in this research. This chapter will explore some of these questions in more detail.
Kenneth M. Butler, M. Ray Mercer
Backmatter
Metadata
Title
Assessing Fault Model and Test Quality
Authors
Kenneth M. Butler
M. Ray Mercer
Copyright Year
1992
Publisher
Springer US
Electronic ISBN
978-1-4615-3606-2
Print ISBN
978-1-4613-6602-7
DOI
https://doi.org/10.1007/978-1-4615-3606-2