Characterization Methods for Submicron MOSFETs

The Metal-Oxide-Semiconductor field effect transistor (MOSFET) is one of the key devices for the fabrication of very (or ultra) large scale integrated circuits in modern microelectronics. The performance of the MOSFET is primarily determined by the quality of the gate dielectrics and that of the Si — SiO₂ interface which directly affects the carrier transport properties. On the other hand, the modeling of the device characteristics requires the rigorous definition of the MOSFET parameters which mainly control the device operation. Furthermore, the design of analog and digital circuits relies on electrical simulations based on SPICE-like programs in which state-of-the-art MOSFET static models have to be implemented in analytical forms. For this reason, the modeling of the submicron MOS transistor is a mandatory issue for the development of new CMOS circuits and semiconductor memories. Besides, the static measurements and the corresponding parameter extraction of MOSFETs have proved to be a powerful and simple characterization tool even though they are not competing with other electrical techniques also presented in this book.

The performance of an MOS transistor is determined to a great extent by the quality of its Si — SiO₂ interface. During the early stages of development of MOS technology, the MOS capacitor has been used as the principal tool for investigating and understanding the properties of the MOS system [1–8]. In fact, much of the present knowledge of the properties of this system has been acquired by small signal admittance measurements on MOS capacitors. As pointed out by Nicollian and Brews [9], more than 20 properties of the MOS system can be measured and monitored using MOS capacitors.

The interface between the silicon substrate and the gate oxide in the active region of a MOS transistor plays a crucial role in determining the device parameters and affects reliability and lifetime of the device. The measurement and characterization of the interface properties are needed to understand the origin and physical properties of the interface states in an MOS system. Interface states can capture and emit charge carriers and the amount of charge in the interface states determines the device parameters. Interface state measurements are routinely carried out on test devices to monitor the manufacturing process as well as to study the lifetime and reliability of the devices. The interface measurements are also used in failure analysis investigations. The usual technique to study interface characteristics is to use a large area MOS capacitor with the gate oxide grown at the same time or in similar circumstances as when the gate oxide in the product device is grown. The Capacitance-Voltage (C-V) characteristics of the capacitor are analyzed to obtain the energy distribution of fast interface state density, fixed oxide charge and slow interface state density. Fast interface states are those which are located just at the interface and therefore can readily exchange charge with the substrate by capturing and emitting charge carriers. The amount of charge residing in the fast interface states is a function of the surface potential or band-bending and therefore a function of the gate voltage.

Many semiconductor defects manifest themselves through deep and shallow levels in the energy gap. Deep levels may act as electron or hole traps depending on their state of occupancy. Shallow levels are formed in semiconductor crystals when a foreign atom, which belongs to the groups of the periodic table closest to that of the semiconductor, is introduced into the lattice. These shallow levels are used to control the concentartion of holes or electrons in the semiconductor. They can be described by the effective mass theory of Kohn and Luttinger [1], giving a hydrogen like spectrum of the discrete levels with the binding energies E _n , which can be written as: where m* is an effective mass for the electron or hole, 2208 is the static dielectric constant of the semiconductor, and n is an integer. For the ground state energies, better agreement between calculated and measured values are obtained using a more complicated pseudo-impurity theory developed by Pantelides [2].

The immense progress in silicon technology and miniaturization of electronic devices to sub-micrometer sizes has led to almost defect-free metal oxide semiconductor field effect transistors (MOSFETs). The centerpiece of microelectronics technology, the Si — SiO₂ interface, is today fabricated with an interface trap density D_it = 10⁸ − 10¹⁰ cm^-2eV^-1, so that a standard MOSFET with sub-μm gate dimensions contains less than 1–100 defects in its active area. A schematic of an n-channel MOSFET is depicted in Figure 5.1(a). The carrier densities induced in the channel by the variable gate bias voltage range from n_s = 10⁹ cm^-2 in the sub-threshold bias region up to n_s = 10¹² cm^-2 for high gate bias voltages. The number of charge carriers in the channel of a micrometer-sized MOSFET therefore ranges from about 10 in the sub-threshold region up to more than 10000 electrons in strong inversion. Capture of a single electron into an interface trap causes a noticeable 0.01% to 10% change in the number of mobile charge carriers in the channel and thus in its conductance. Conductance changes of the channel may be even larger, because the mobility is also affected by the trapping or emission of a charge carrier due to the creation or annihilation of a scattering center. Trapping and re-emission of single electrons from and to the channel by interface traps cause a random switching of the source-drain conductance between two discrete states, as schematically sketched out in Figure 5.1(b).

After a long period of maturation, SOI technology has reached a stage of rapid and successful development. A major condition for competing with bulk silicon in commercial applications is the degree of understanding of material properties, fabrication techniques, and device operation. This implies the use of adequate characterization methods which overcome the difficulties induced by the thinness of the film and by the stacked interfaces. Since the quality of SOI structures has considerable impact on the performance of integrated circuits, reciprocally the devices may be interrogated on the properties of the starting material and the process-induced modifications.

The integrated circuit technology used in very large scale integrated (VLSI) circuit fabrication of digital circuits has been employed to realize purely analog circuits or mixed signal (digital and analog) circuits. In contrast to the digital counterpart, high precision analog circuit performance is strongly dependent on the accuracy of the element matching. Typical elements that are used in analog CMOS design are PMOS/NMOS transistors, MOS capacitors and resistors. Therefore, the characterization and modeling of these elements are of paritcular importance for CMOS analog circuit design. The basic characterization techniques are covered in other publications such as [1], [2] and [3]. This chapter discusses a number of characterization techniques which address the special concerns of analog circuit designers such as transistor matching, resistance matching and base spreading resistance extraction for BJT.