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2012 | OriginalPaper | Chapter

4. Chip Implementations

Authors : Kunio Uchiyama, Fumio Arakawa, Hironori Kasahara, Tohru Nojiri, Hideyuki Noda, Yasuhiro Tawara, Akio Idehara, Kenichi Iwata, Hiroaki Shikano

Published in: Heterogeneous Multicore Processor Technologies for Embedded Systems

Publisher: Springer New York

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Abstract

Three prototype multicore chips, RP-1, RP-2, and RP-X, were implemented with the highly efficient cores described in Chap. 3. The details of the chips are described in this chapter. The multicore architecture makes it possible to enhance the performance while maintaining the efficiency, but not to enhance the efficiency. Therefore, a multicore with inefficient cores is still inefficient, and the highly efficient cores are the key components to realize a high-performance and highly efficient SoC. However, the multicore requires different technologies from that of a single core to maximize its capabilities. The prototype chips are useful for researching and developing such technologies and have been utilized for developing and evaluating software environments, application programs, and systems (see Chaps. 5 and 6).

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previous chapter Processor Cores
next chapter Software Environments
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Metadata
Title
Chip Implementations
Authors
Kunio Uchiyama
Fumio Arakawa
Hironori Kasahara
Tohru Nojiri
Hideyuki Noda
Yasuhiro Tawara
Akio Idehara
Kenichi Iwata
Hiroaki Shikano
Copyright Year
2012
Publisher
Springer New York
Book
Heterogeneous Multicore Processor Technologies for Embedded Systems

Print ISBN: 978-1-4614-0283-1

Electronic ISBN: 978-1-4614-0284-8

Copyright Year: 2012

DOI
https://doi.org/10.1007/978-1-4614-0284-8_4