Advertisement
Published in:
2018 | OriginalPaper | Chapter
4. Circuit Vulnerabilities to Hardware Trojans at the Gate Level
Author : Hassan Salmani
Published in: Trusted Digital Circuits
Publisher: Springer International Publishing
Activate our intelligent search to find suitable subject content or patents.
Select sections of text to find matching patents with Artificial Intelligence. powered by
Select sections of text to find additional relevant content using AI-assisted search. powered by
Abstract
A gate-level netlist is a description of the connectivity of a circuit. To meet design constraints such as time to market and product cost, gate-level netlists as firm IPs are commonly used for complex circuits implementation. Meanwhile, not all entities providing gate-level netlists are trusted and they may modify expected circuit functionality or use unused portions of a circuit to realize a hardware Trojan. Therefore, there is a serious demand to gate-level vulnerability analyses and security metrics to determine hard-to-detect areas in a circuit that would most probably be used for hardware Trojan implementation to ensure the hardware Trojan goes undetected during production test and extensive functional test analyses.