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Challenges and Opportunities in VLSI for Systems Dependability Read chapter Read first chapter

2019 | OriginalPaper | Chapter

8. Connectivity in Electronic Packaging

Authors : Hiroki Ishikuro, Tadahiro Kuroda, Atsutake Kosuge, Mitsumasa Koyanagi, Kang Wook Lee, Hiroyuki Hashimoto, Makoto Motoyoshi

Published in: VLSI Design and Test for Systems Dependability

Publisher: Springer Japan

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Abstract

This chapter deals with the issue of packaging and interconnects in electronic systems. An electronic system in general consists of multiple subsystem modules in certain form of packages and electrical interconnects between them. A module, in turn, consists of multiple VLSI chips and interconnects. Interconnects often become bottleneck of the performance of electronic systems because the performance gap between the bus bandwidth and processor core speed has increased as the process technology scales. Development in the performance of systems has thus been accompanied by the development of interconnects as well as VLSI chips. Exactly like what happened in the VLSI, the technology of packaging and interconnects has developed tremendously in terms of bandwidths, power dissipation, form factors (physical dimensions), and so forth. In fact, it has always been one of the central issues in the design of systems, involved sophisticated engineering, and required attention from the perspective of dependability. Section 8.1 gives an overview of the requirements for packaging and interconnects and highlights wireless technology for packaging as an emerging technology for packaging or integrating complex systems. Section 8.2 introduces wireless interconnect and compares it with conventional wired interconnect in a few practical examples. Section 8.3 describes the through-silicon via (TSV) in three-dimensional (3D) integration of silicon VLSI from the perspective of performance and dependability and introduces the concept of redundant vias.

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Literature
1.
J. Lee et al., A low-power fully integrated 60 GHz transceiver system with OOK modulation and on-board antenna assembly, in IEEE International Solid-State Circuits Conference (ISSCC’09). Digest of Technical Papers, February 2009, pp. 316–317
2.
Y. Tanaka et al., A versatile multi-modality serial link, in IEEE International Solid-State Circuits Conference (ISSCC’12). Digest of Technical Papers, February 2012, pp. 332–333
3.
T. Abe et al., A 2 Gb/s 150 mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme, in IEEE International Solid-State Circuits Conference (ISSCC’12). Digest of Technical Papers, February 2012, pp. 442–443
4.
M. Tamura et al., A 1 V 357 Mb/s-throughput transferjet™ SoC with embedded transceiver and digital baseband in 90 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC’12). Digest of Technical Papers, February 2012, pp. 440–441
5.
S. Kawai et al., A 2.5 Gb/s/ch inductive-coupling transceiver for non-contact memory card, in IEEE International Solid-State Circuits Conference (ISSCC’10). Digest of Technical Papers, February 2010, pp. 264–265
6.
H. Cho et al., A 1.2 Gb/s 3.9 pJ/b, mono-phase pulse-modulation inductive-coupling transceiver for mm-range board-to-board communication, in IEEE International Solid-State Circuits Conference (ISSCC’13). Digest of Technical Papers, February 2013, pp. 202–203
7.
K. Hijioka et al., A 5.5 Gb/s 5 mm contactless interface containing a 50 Mb/s bidirectional sub-channel employing common-mode OOK signaling, in IEEE International Solid-State Circuits Conference (ISSCC’13). Digest of Technical Papers, February 2013, pp. 406–407
8.
K. Ikeuchi et al., 500 Mbps, 670 μW/pin capacitively coupled receiver with self reset scheme for wireless connectors, in IEEE Asian Solid-State Circuits Conference (A-SSCC’08). Digest of Technical Papers, November 2008, pp. 93–96
9.
T. Takeya et al., A 12 Gb/s non-contact interface with coupled transmission lines, in IEEE International Solid-State Circuits Conference (ISSCC’11). Digest of Technical Papers, February 2011, pp. 492–493
10.
W.-J. Yun et al., A 7 Gb/s/Link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line, in IEEE International Solid-State Circuits Conference (ISSCC’12). Digest of Technical Papers, February 2012, pp. 52–53
11.
W. Mizuhara et al., A 0.15 mm-thick non-contact connector for MIPI using vertical directional coupler, in IEEE International Solid-State Circuits Conference (ISSCC’13). Digest of Technical Papers, February 2013, pp. 200–201
12.
A. Kosuge et al., An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%, in IEEE International Solid-State Circuits Conference (ISSCC’14). Digest of Technical Papers, February 2014, pp. 496–497
13.
R. Shinoda et al., Voltage-boosting wireless power delivery system with fast load tracker by ΔΣ-modulated sub-harmonic resonant switching, in IEEE International Solid-State Circuits Conference (ISSCC’12). Digest of Technical Papers, February 2012, pp. 288–289
14.
K. Tomita et al., 1 W 3.3 V-to-16.3 V boosting wireless power transfer circuits with vector summing power controller, in IEEE Asian Solid-State Circuits Conference (ASSCC’11). Digest of Technical Papers, November 2011, pp. 177–180
15.
Y. Hasegawa et al., Single-inductor-dual-output wireless power receiver with synchronous pseudo-random-sequence PWM switched rectifiers, in IEEE Asian Solid-State Circuits Conference (A-SSCC’13). Digest of Technical Papers, November 2013, pp. 261–264
16.
H. Ishikuro, T. Kuroda, Wireless proximity interfaces with a pulse-based inductive coupling technique. IEEE Commun. Mag. 48(10), 192–199 (2010)CrossRef
17.
M. Saito, N. Miura, T. Kuroda, A 2 Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking, in IEEE International Solid-State Circuits Conference (ISSCC). Digest of Technical Papers, February 2010, pp. 440–441
18.
K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, I. Nonomura, M. Saen, S. Komatsu, K. Osada, N. Irie, T. Hattori, A. Hasegawa, T. Kuroda, An inductive-coupling link for 3D integration of a 90 nm CMOS processor and a 65 nm CMOS SRAM, in IEEE International Solid-State Circuits Conference (ISSCC’09). Digest of Technical Papers, February 2009, pp. 480–481
19.
Y. Kohama, Y. Sugimori, S. Saito, Y. Hasegawa, T. Sano, K. Kasuga, Y. Yoshida, K. Niitsu, N. Miura, H. Amano, T. Kuroda, A scalable 3D processor by homogeneous chip stacking with inductive-coupling link, in 2009 Symposium on VLSI Circuits. Digest of Technical Papers, June 2009, pp. 94–95
20.
S. Kawai, H. Ishikuro, T. Kuroda, A 4.7 Gb/s inductive coupling interposer with dual mode modem, in 2009 Symposium on VLSI Circuits. Digest of Technical Papers, June 2009, pp. 92–93
21.
U. Kang et al., 8 Gb 3D DDR3 DRAM using through-silicon-via technology, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), February 2009, pp. 130–131
22.
H. Yoshikawa et al., Chip scale camera module (CSCM) using through-silicon-via (TSV), in IEEE International Solid-State Circuits Conference (ISSCC). Digest of Technical Papers, February 2009, pp. 476–477
23.
B. Razavi, RF Microelectronics, 2nd edn., Chap. 3 (Prentice Hall, 2011)
24.
H. Ishikuro, T. Sugahara, T. Kuroda, An attachable wireless chip access interface for arbitrary data rate using pulse-based inductive-coupling through LSI package, in IEEE International Solid-State Circuits Conference (ISSCC). Digest of Technical Papers, February 2007, pp. 360–361
25.
D. Mizoguchi, Y.B. Yusof, N. Miura, T. Sakurai, T. Kuroda, A 1.2 Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS), in IEEE International Solid-State Circuits Conference (ISSCC). Digest of Technical Papers, February 2004, pp. 142–143
26.
N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, A 1 Tb/s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link. IEEE J. Solid-State Circuits 42(1), 111–122 (2007)
27.
A. Fazzi, L. Magagni, M. Mirandola, B. Charlet, L. Di Cioccio, E. Jung, R. Canegallo, R. Guerrieri, 3-D capacitive interconnections for wafer-level and die-level assembly. IEEE J. Solid-State Circuits 42(10), 2270–2282 (2007)
28.
M. Koyanagi, in 8th Symposium on Future Electron Devices (1989), pp. 50–60
29.
T. Matsumoto, M. Koyanagi et al., in International Conference on Solid State Devices and Materials (SSDM) (1995), pp. 1073–1074
30.
31.
32.
P. Ramm et al., in International Interconnect Technology Conference (IITC) (2001), pp. 160–162
33.
J. Burns et al., in International Solid State Circuits Conference (ISSCC) (2001), pp. 268–269
34.
M. Bohr, in International Electron Devices Meeting (IEDM). Technical Digest (2011), pp. 1–4
35.
M. Koyanagi, in International Electron Devices Meeting IEDM. Technical Digest (2013), pp. 8–15
36.
M. Koyanagi et al., in International Solid State Circuits Conference (ISSCC) (2001), pp. 270–271
37.
H. Kurino, M. Koyanagi et al., in International Electron Devices Meeting (IEDM) (1999), pp. 879–882
38.
K.W. Lee, M. Koyanagi et al., in International Electron Devices Meeting (IEDM) (2000), pp. 165–168
39.
T. Ono, M. Koyanagi et al., in International Symposium on Low-Power and High-Speed Chips (COOL Chips V) (2002), pp. 186–193
40.
M. Koyanagi et al., IEEE Trans. Electron Devices 53(11), 2799–2808 (2006)CrossRef
41.
M. Koyanagi et al., Proc. IEEE 97(1), 49–59 (2009)
42.
M. Murugesan, M. Koyanagi et al., in International Electron Devices Meeting (IEDM) (2011), pp. 139–142
43.
J.-C. Bea, M. Koyanagi et al., IEEE Electron Device Lett. 32(1), 66–68 (2011)CrossRef
44.
J.-C. Bea, M. Koyanagi et al., IEEE Electron Device Lett. 32(7), 940–942 (2011)CrossRef
45.
K.-W. Lee, M. Koyanagi et al., IEEE Electron Device Lett. 33(9), 1297–1299 (2012)CrossRef
46.
H. Kino, M. Koyanagi et al., Jpn. J. Appl. Phys. 52(4, 2), 04CB11-1–04CB11-6 (2013)
47.
K.-W. Lee, M. Koyanagi et al., IEEE Electron Devices Lett. 34(8), 1038–1040 (2013)CrossRef
48.
H. Hashimoto, M. Koyanagi et al., in International Conference on Solid State Devices and Materials (SSDM) (2011), pp. 168–169
49.
L. Jiang et al., IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 559–571 (2013)
50.
H. Hashimoto, M. Koyanagi et al., IEEE 3DIC, October 2013
Metadata
Title
Connectivity in Electronic Packaging
Authors
Hiroki Ishikuro
Tadahiro Kuroda
Atsutake Kosuge
Mitsumasa Koyanagi
Kang Wook Lee
Hiroyuki Hashimoto
Makoto Motoyoshi
Copyright Year
2019
Publisher
Springer Japan
Book
VLSI Design and Test for Systems Dependability

Print ISBN: 978-4-431-56592-5

Electronic ISBN: 978-4-431-56594-9

Copyright Year: 2019

DOI
https://doi.org/10.1007/978-4-431-56594-9_8