Contextual Constraints for Design and Verification

A new approach to the design and verification of VLSI structures capitalizing on knowledge of the surrounding environment is proposed. This approach formalizes the use of contextual information as a means of simplifying the design and verification process and provides us with a new way of viewing the hierarchical evolution of a design. The proposed design process illustrates the different uses of contextual constraints to aid and guide the designer. In particular, constraints may be introduced to simplify verification and must in turn be satisfied by the design itself. Hence we find that design choices may be made to aid validation, an interesting reversal in the usual post-design role of simulation and formal verification.