Copper Electrodeposition for Nanofabrication of Electronics Devices

Copper sulfate (CuSO₄·5H₂O) and sulfuric acid (H₂SO₄) are the primary constituents of the Acid copper sulfate bath [1]. The formulation of the bath is adjusted depending on the intended use, as given in Table 1.1.

The excellent additive systems for acid copper sulfate bath developed in the 1960s successfully produce bright copper deposits with smooth surfaces and high ductility. Since then, many applications of copper plating were developed for electronic device and through-hole plating for PCBs as well as conventional decorative plating on steel, electroforming, etc.

Fabrication of microscale and nanoscale structures can be implemented by electrodeposition of copper onto conductive templates that contain recesses in form of the desired structure. The current distribution that results from deposition from a simple acid copper solution is concentrated near the upper corners of recesses and results in incomplete filling, formation of voids, and a substantial overburden of nonfunctional material.

This chapter is devoted to recent developments in mathematical modeling and computer simulation of copper electrodeposition. We focus our attention on continuum models and kinetic Monte Carlo simulations for shape evolution and the effects of additives on copper deposition, especially the filling of small features in microelectronics. The modeling, mathematical treatments, and simulation results are reviewed with brief summaries of efficient numerical algorithms. Fast computing and prospects of simulation research are also discussed.

In the electronics industry, interconnect is defined as a conductive connection between two or more circuit elements. It interconnects elements (transistor, resistors, etc.) on an integrated circuit or components on a printed circuit board. The main function of the interconnect is to contact the junctions and gates between device cells and input/output (I/O) signal pads. These functions require specific material properties. For performance or speed, the metallization structure should have low resistance and capacitance. For reliability, it is important to have the capability of carrying high current density, stability against thermal annealing, resistance against corrosion and good mechanical properties.

The evolution of copper microstructure and incorporated impurities was studied using transmission electron microscopy (TEM), secondary ion mass spectroscopy (SIMS), and electrical resistance measurements for narrow (~28–40 nm) and wide Damascene features. Resistance measurements suggest an increasing degree of post-CMP microstructure evolution with anneal as linewidth falls below 100 nm for both “doped” and “pure” electrodeposited Cu. SIMS shows increased levels of incorporated sulfur and chlorine in narrow Cu lines whose concentration distributions appear unaffected by annealing at 350 °C, in contrast to redistribution observed in wider lines. Wide lines exhibit significant grain growth with a high temperature anneal, while little to no grain growth is evident upon anneal in narrow line longitudinal TEM sections. This post-anneal resistance drop and concomitant lack of recrystallization and grain growth in the narrow Cu lines is consistent with a microstructure recovery process, where defects in the Cu lattice are eliminated without appreciable formation and growth of new grains.

Direct plating is the term used in the damascene interconnect technology when copper (Cu) is plated on a substrate without a copper seed. The conductive copper seed is replaced by a nobler metal such as ruthenium (Ru) or metal compounds such as RuTa or RuTiN alloys in an effort to combine seed and barrier properties into one as the lining thin film material [1]. Copper electrodeposition on top of a foreign substrate by itself is of course not that unusual, copper plated on a platinum rotating disk electrode is quite standard in the lab, but there are many technological complications when bringing it to the wafer scale. In contrast to the conductive platinum disk in the lab, the thin barrier and seed lining layers are resistive which implies a significant potential drop from the wafer edge to the wafer center.

The development of semiconductor devices is clearly represented by Moor’s law. Moor’s law, formulated by Gordon Moor at Intel, predicts that the semiconductor transistor number is doubled every 1.5 years, and this trend has held since the birth of the Intel microprocessor 4004 in 1965. Because of the limits of miniaturization in transistor fabrication, deviation from Moor’s law in recent years has become an obstacle to the development of semiconductor devices.

Build-up printed wiring boards (build-up PWBs) are advanced forms of plated through hole printed wiring boards (PTH PWBs). Not only build-up PWBs but also PTH PWBs are based on the technologies used to achieve high density and multilayer PWBs, which are currently demanded. Build-up PWBs are considered to improve on the weak points of PTH PWBs. In order to achieve more advanced high density PWBs, progressive manufacturing technologies have been introduced. One of the most important technologies is filled via copper deposition, as mentioned in the previous chapters. The filled vias can be stacked on the vias in the lower layer, resulting in better electrical performance and greater wiring density than those achieved with conformal vias. Therefore the application of via filling is expanding. The details are described later in Sect. 9.7.3.

An electrodeposited copper foil has been used in many areas of printed-wiring boards, such asrigid printed-wiring boards and flexible printed-wiring boards, as shown in Fig. 10.1. Even now, it is estimated that more than 90 % of all the electrodeposited copper foil production is being used for printed-wiring boards.On the other hand,the use of ekectrodeposited copper foil as the negative electrode collector of lithium-ion batteries has recently been attracting attention.The time when the electrodeposited copper foil came into use in this field was comparatively recent, i.e. in the latter half of the 1990s. Many lithium-ion batteries are being used for mobile phones, smart phones, notebook personam computers,etc. In addition, major automakers around the world are currently studying its use in EV, HEV, PHEV, etc.

Plated through hole (PTH) is an age-old process technology, especially in the fabrication of printed circuit boards (PCBs). However, PTH is still employed currently for advanced PCB fabrication. The main differences between the conventional PTHs and the current PTHs are acceptable criteria of process and reliability.