Advertisement
Published in:
2017 | OriginalPaper | Chapter
Design and FPGA Implementation of 32-Point FFT Processor
Authors : Amit Kumar, Adesh Kumar, Aakanksha Devrari, Shraddha Singh
Published in: Proceeding of International Conference on Intelligent Communication, Control and Devices
Publisher: Springer Singapore
Activate our intelligent search to find suitable subject content or patents.
Select sections of text to find matching patents with Artificial Intelligence. powered by
Select sections of text to find additional relevant content using AI-assisted search. powered by
Abstract
The research article presents the design and FPGA implementation of 32-point FFT algorithm. DFT has the symmetry and periodicity property, but requires more hardware, delay for the calculations in butterfly structure because twiddle factor is loaded in each stage. Twiddle factor has the real and imaginary parts and utilize inefficient memory. FFT computation requires less number of clock cycles because the periodicity and symmetry property of the twiddle factors in several stages together optimize the memory utilization and storage area due to twiddle factors. In the research article 32-point FFT processor is designed using VHDL programming language. It is based on pipelined architecture and can be used for high-speed applications and modulation techniques like Orthogonal Frequency Division Multiplexing in 4G mobile communication. The design is carried in Xilinx ISE 14.2 and functional checked in Modelsim 10.1 and synthesized on Virtex 5 FPGA.