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2018 | OriginalPaper | Chapter

Design of High-Speed LVDS Data Communication Link Using FPGA

Authors : Shraddha Shukla, Jitendra P. Chaudhari, Rikin J. Nayak, Hiren K. Mewada

Published in: Information and Communication Technology for Intelligent Systems (ICTIS 2017) - Volume 2

Publisher: Springer International Publishing

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Abstract

This paper proposed the design and implementation of high speed communication link between two FPGAs using LVDS driver using 100 MHz clock. Initially Asynchronous and Synchronous communication are discussed and then synchronous communication is used for LVDS data communication. The speed of the communication is sensitive to the noise and sampling of the data at the receiver end. Therefore, the differential signal voltage level and sampling at the falling edge of clock are proposed in the design to maintain the high speed.

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next chapter Face Super Resolution by Tangential and Exponential Kernel Weighted Regression Model
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Metadata
Title
Design of High-Speed LVDS Data Communication Link Using FPGA
Authors
Shraddha Shukla
Jitendra P. Chaudhari
Rikin J. Nayak
Hiren K. Mewada
Copyright Year
2018
Book
Information and Communication Technology for Intelligent Systems (ICTIS 2017) - Volume 2

Print ISBN: 978-3-319-63644-3

Electronic ISBN: 978-3-319-63645-0

Copyright Year: 2018

DOI
https://doi.org/10.1007/978-3-319-63645-0_1

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