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IEEE 754 Floating Point Pipelined Multiplier with Karatsuba for Mitigations of Area and Power Read chapter Read first chapter

2021 | OriginalPaper | Chapter

Digital Fault Detection Techniques: A Review

Authors : Vivekananda Mukherjee, Pradip Kumar Ghosh, Manabendra Maiti, Judhajit Sanyal

Published in: Computers and Devices for Communication

Publisher: Springer Singapore

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Abstract

The testing and detection of faults in digital circuits has become extremely relevant to both industry as well as academia in recent years. Effective and cheap testing procedures and algorithms help to decrease the manufacturing costs for digital circuits to a significant extent. The present work discusses state-of-the-art digital fault detection techniques. Specific emphasis is laid on a relatively new class of techniques that employ machine learning techniques to classify and detect faults in digital circuits and systems, especially focusing on Bayesian networks and support vector machines (SVMs). The work is concluded by the proposal of a machine learning-based fault probability estimation technique and brief deliberations on the enhancements that can be made in future to the technique.

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Metadata
Title
Digital Fault Detection Techniques: A Review
Authors
Vivekananda Mukherjee
Pradip Kumar Ghosh
Manabendra Maiti
Judhajit Sanyal
Copyright Year
2021
Publisher
Springer Singapore
Book
Computers and Devices for Communication

Print ISBN: 978-981-15-8365-0

Electronic ISBN: 978-981-15-8366-7

Copyright Year: 2021

DOI
https://doi.org/10.1007/978-981-15-8366-7_2