IEEE 754 Floating Point Pipelined Multiplier with Karatsuba for Mitigations of Area and Power

The proposed architecture implements IEEE 754 floating point pipelined multiplier merge single and double precision using Karatsuba. This paper is presented in order to reduce power and area expenditures to fast the process of the adder and reduce delay. To achieve, the design Verilog language is used and targeted on Xilinx Virtex-5 (XC5VLX155FF1760-3) and Cadence on TSMC-180 nm CMOS technology. The architecture reduces the processing block as it uses exception block as replacement, whereas in the Karatsuba multiplier, the adders are replaced with different adder to obtain reduce results of area and power. Karatsuba is used in placing the mantissa in the multiplier, and in the Karatsuba architecture, the previous design is replaced in order to reduce the numbers of operations in block processing; here, left shifting is in the 27 * 27 bits multiplier. By implementation of various adders, better results are obtained when compared to the previous work in terms of DSP 6 (4%), LUTs 1367 (1%), frequency 168.741 MHz, dynamic power 123.61 mW.