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2021 | OriginalPaper | Chapter

Efficient Memory Parity Check Matrix Optimization for Low Latency Quasi Cyclic LDPC Decoder

Authors : Mhammed Benhayoun, Mouhcine Razi, Anas Mansouri, Ali Ahaitouf

Published in: Proceedings of the 2nd International Conference on Electronic Engineering and Renewable Energy Systems

Publisher: Springer Singapore

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Abstract

Implementation of Low Density Parity Check (LDPC) decoders using conventional algorithms such as LLR BP or Min-Sum requires large amount of memory resources for storing the parity check matrix. This paper presents a soft implementation of irregular LDPC decoding for Wimax application, which achieve better BER performance and faster convergence with less memory requirement. The proposed construction reduce the memory required for loading the LDPC parity-check matrix by up to 98%, and subsequently reduce the decoding latency to 0.7 ms by iteration.

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Metadata
Title
Efficient Memory Parity Check Matrix Optimization for Low Latency Quasi Cyclic LDPC Decoder
Authors
Mhammed Benhayoun
Mouhcine Razi
Anas Mansouri
Ali Ahaitouf
Copyright Year
2021
Publisher
Springer Singapore
Book
Proceedings of the 2nd International Conference on Electronic Engineering and Renewable Energy Systems

Print ISBN: 978-981-15-6258-7

Electronic ISBN: 978-981-15-6259-4

Copyright Year: 2021

DOI
https://doi.org/10.1007/978-981-15-6259-4_5