Enhanced Spanning-Tree Adder Structures Using Carry Increment Adders

This paper is aimed primarily at reducing the overall amount of time and increasing efficiency on FPGA platforms. They are proving their applicability in high-performance computing to decide the field of FPGA’s use. The paper defines the tree adder with variable data path sizes of eight bits to 64 bits, which is the parallel implementation prefix. VHDL was used to develop P.P.A. topology, and Xilinx was synthesized with the FPGA chip machine. Intensive experiments and measurements have been performed, and design costs such as total path delay time and the use of hardware have been checked and assessed. The results for code synthesis demonstrated the best values of delays for spanning tree adder, which was suggested over the existing method Price and Stine (IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), pp 223–226, 2019 [1]), which has brought new creativity in the field of digital arithmetic. Such designs take the best part of many applications and improve performance in terms of area and delay. This work implements a 64-bit hybrid adder with the carrying increment algorithm using a spanning tree structure. In contrast to an existing design, the results showed promising data.