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2018 | OriginalPaper | Chapter

FPGA-Based Implementation of AES Algorithm Using MIX Column

Authors : S. Neelima, R. Brindha

Published in: Microelectronics, Electromagnetics and Telecommunications

Publisher: Springer Singapore

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Abstract

This article deals with the clear analysis and experimental simulation results of the modified AES-128-bit algorithm which can be personalized. To improve this technique, we introduced the high-level increased parallelism scheme which will reflect even in Mi columns of the AES architecture. By using this technique, we can increase the throughput efficiency and is implemented on Quartus of FPGA device. With this technique, usage can increase the stack usage for 5% more with a minimum reduction of 30% area.

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Title: FPGA-Based Implementation of AES Algorithm Using MIX Column
Authors: S. Neelima
R. Brindha
Publisher: Springer Singapore
Book: Microelectronics, Electromagnetics and Telecommunications
Print ISBN: 978-981-10-7328-1

Electronic ISBN: 978-981-10-7329-8

Copyright Year: 2018
DOI: https://doi.org/10.1007/978-981-10-7329-8_24