FPGA Implementation of Efficient 32-Bit 3-Operand Addition Using Kogge–Stone (KS) Parallel Prefix Adder

For performing efficient modular arithmetic operations, several cryptographic and pseudorandom bit generator (PRBG) algorithms utilize a 3-operand binary adder as the primary functional unit. The Carry Save Adder is the most common adder used for performing the three-operand extension (CS3A). On the other hand, the ripple-carry step of CS3A results in a significant delay while transmitting the output signals. Due to the lengthy delay, it influences the performance of MDCLG architecture. For performing three-operand addition, two-operand adders, such as Kooge Stone (KSA), can be used. This will decrease the critical route latency, delay, and area compared to other parallel prefix adders. The proposed high-speed and space-efficient adder architecture for performing three-operand binary operations includes carry-prefix computation logic after performing the pre-compute bitwise addition. The proposed adder design reduces the adder latency while consuming less area and power. A Kogge–Stone parallel prefix adder has been used to develop a novel architecture for the proposed 8-bit, 16-bit, and 32-bit three-operand adders. The proposed architecture is implemented by using Verilog coding, and further, the power and delay extraction has been performed by using a Xilinx tool. The proposed architecture has been developed by using the MDCLCG method with the three-operand adder, and further, the proposed architecture is proven with respect to delay as well as area and power.