FPGA Performance Evaluation of Present Cipher Using LCC Key Generation for IoT Sensor Nodes

IoT which enables data transmission through different kind’s interrelated networks, mostly the data is exchanged between wireless networks, and chances of hacking. Security is the most important aspect, and the data should be confidential to avoiding hacking. The cryptography solutions are utilized as an answer for improving security and the customary calculations because their limitation setting is not perfect for IoT gadgets. It is therefore possible to use the lightweight cryptographic algorithm as a solution to IoT security problems. However, there are a number of algorithms to choose from the distinctive execution criteria and conditions; the PRESENT cipher template in this paper is the encryption method using the 64-bit key for 64-bit data for hardware-level data protection input. To improve the security, Lorenz Chaotic Circuit with Dual-port Read Only Memory-based Present Algorithm (LCC-DROM-PA) architecture is proposed in this work, and for generating the key value, LCC is an essential design, and DROM is used for S-box design and P-layer design. After designing this architecture, FPGA performances are evaluated by the count of LUTs, flip-flops, slices, and frequency.