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Published in:
2011 | OriginalPaper | Chapter
Global Routing
Authors : Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Published in: VLSI Physical Design: From Graph Partitioning to Timing Closure
Publisher: Springer Netherlands
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During
global routing
, pins with the same electric potential are connected using wire segments. Specifically, after
placement
(Chap. 4), the layout area is represented as
routing regions
(Sec. 5.4) and all nets in the netlist are routed in a systematic manner (Sec. 5.5). To minimize total routed length, or optimize other objectives (Sec. 5.3), the route of each net should be short (Sec. 5.6). However, these routes often compete for the same set of limited resources. Such conflicts can be resolved by concurrent routing of all nets (Sec. 5.7), e.g.,
integer linear programming (ILP)
, or by sequential routing techniques, e.g.,
rip-up and reroute
. Several algorithmic techniques enable scalability of modern global routers (Sec. 5.8).