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2024 | OriginalPaper | Chapter

3. Hardware and Environment Modeling

Authors : Pascal Pieper, Rolf Drechsler

Published in: Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes

Publisher: Springer Nature Switzerland

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Abstract

This chapter explores the role of RISC-V in the Internet of Things (IoT) era, emphasizing its popularity due to its open and free instruction set architecture. The chapter introduces virtual prototypes (VPs) as a crucial tool, addressing the gap between early system design and fully finished systems. It presents a RISC-V based VP that supports multi-core platforms, operating systems, and offers faster simulation compared to RTL. The discussion extends to an Environment Model GUI for simulation of off-chip devices, and a debugging visualization tool called RISCVIEW, and a method to bridge the TLM/RTL gap in SoC design using Hardware-in-the-Loop (HWITL) simulations with FPGAs. The proposed VPIL strategy enables early Design Space Exploration (DSE) and validation, enhancing the efficiency of SoC development. The chapter concludes with suggestions for further extensions to the approach for specialized applications.

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previous chapter Preliminaries

next chapter Verification

In particular, the freely available RISC-V port of GDB, which knows about the available RISC-V register set, the CSRs, and can provide a disassembly of the RISC-V instruction set.

Early tests have shown that instantiating one Lua state per device results a prohibitively high memory usage already in small numbers of devices and also significantly reduces the execution speed.

This is a technical limitation of the used LuaBridge3, in where C functions may only be global.

To optimize the communication protocol, some SPI devices use a separate input pin to incoming bytes as data or commands.

Note that the RISC-V VP has the feature to lock the CLINT’s internal timer to either simulation or wall clock time.

Refresh rate in all tests varied between 10 and 20 Hz, limited to 20 Hz.

B. Menhorn, F. Slomka, Confirming the design gap, in Advances in Computational Science, Engineering and Information Technology, ed. by D. Nagamalai, A. Kumar, A. Annamalai (Springer International Publishing, Heidelberg, 2013), pp. 281–292. ISBN: 978-3-319-00951-3CrossRef

Semiconductor Industry Association. 2008 International Technology Roadmap for Semiconductors (ITRS) (2008) [Online]. Available: https://cseweb.ucsd.edu/classes/wi09/cse242a/itrs/ORTC.pdf (visited on 2022-11)

J. Henkel, Embedded computing - closing the SoC design gap. Computer 36(9), 119–121 (2003). https://doi.org/10.1109/mc.2003.1231200.CrossRef

1666-2011 - IEEE Standard for Standard Systemc Language Reference Manual (IEEE, Piscataway, 2012), pp. 1–638. https://doi.org/10.1109/IEEESTD.2012.6134619

R. Leupers et al., Virtual platforms: breaking new grounds, in 2012 Design, Automation and Test in Europe Conference and Exhibition (DATE) (2012), pp. 685–690. https://doi.org/10.1109/DATE.2012.6176558

16.

A. Waterman, K. Asanović, The RISC-V Instruction Set Manual; Volume I: User-Level ISA (RISC-V Foundation, Berkeley, 2019). https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-118.pdf; https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf

17.

A. Waterman, K. Asanović, The RISC-V Instruction Set Manual; Volume II: Privileged Architecture (RISC-V Foundation, Berkeley, 2019). https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-161.pdf

18.

RISC-V calling convention (2018) [Online]. Available: https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf (visited on2018-05)

32.

S. Tempel, V. Herdt, R. Drechsler, An effective methodology for integrating concolic testing with systemc-based virtual prototypes, in 2021 Design, Automation and Test in Europe Conference and Exhibition (DATE) (2021), pp. 218–221. https://doi.org/10.23919/DATE51398.2021.9474149

34.

J. Zielasko, S. Tempel, V. Herdt, R. Drechsler, 3D visualization of symbolic execution traces, in Forum on Specification and Design Languages (2022), pp. 1–8. https://doi.org/10.1109/FDL56239.2022.9925664

35.

V. Herdt, D. Große, S. Tempel, R. Drechsler, Adaptive simulation with virtual prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. 116, 102135 (2021). ISSN: 1383-7621. https://doi.org/10.1016/j.sysarc.2021.102135 [Online]. Available: https://www.sciencedirect.com/science/article/pii/S1383762121001016

38.

V. Herdt, D. Große, P. Pieper, R. Drechsler, RISC-V based virtual prototype: an extensible and configurable platform for the system-level. J. Syst. Archit. 109, 101756 (2020). ISSN: 1383-7621. https://doi.org/10.1016/j.sysarc.2020.101756CrossRef

39.

P. Pieper, V. Herdt, R. Drechsler, Advanced environment modeling and interaction in an open source RISC-V virtual prototype, in Proceedings of the Great Lakes Symposium on VLSI 2022, ser. GLSVLSI ’22, Irvine (Association for Computing Machinery, New York, 2022), pp. 193–197. ISBN: 9781450393225. https://doi.org/10.1145/3526241.3530374

40.

P. Pieper, V. Herdt, R. Drechsler, Advanced embedded system modeling and simulation in an open source RISC-V virtual prototype. J. Low Power Electron. Appl. 12(4) (2022). ISSN: 2079-9268. https://doi.org/10.3390/jlpea12040052 [Online]. Available: https://www.mdpi.com/2079-9268/12/4/52

42.

M. Koenig, R. Rasch, Digital teaching an embedded systems course by using simulators, in 2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) (2021), pp. 1–7. https://doi.org/10.1109/WCAE53984.2021.9707146

43.

Renode, (2022) [Online]. Available: https://renode.io/ (visited on2022-04)

44.

P. Pieper, R. Wimmer, G. Angst, R. Drechsler, Minimally invasive HW/SW co-debug live visualization on architecture level, in Proceedings of the 2021 on Great Lakes Symposium on VLSI, ser. GLSVLSI ’21, Virtual Event (Association for Computing Machinery, New York, 2021), pp. 321–326. ISBN: 9781450383936. https://doi.org/10.1145/3453688.3461524

45.

P. Pieper, V. Herdt, D. Große, R. Drechsler, Dynamic information flow tracking for embedded binaries using SystemC-based virtual prototypes, in 2020 57th ACM/IEEE Design Automation Conference (DAC) (2020), pp. 1–6. https://doi.org/10.1109/DAC18072.2020.9218494

46.

P. Pieper, V. Herdt, R. Drechsler, Verifying SystemC TLM peripherals using modern C++ symbolic execution tools, in 2022 59th ACM/IEEE Design Automation Conference (DAC) (2022), pp. 1–6. https://doi.org/10.1145/3489517.3530604

48.

P. Pieper, Virtual breadboard GUI (2022) [Online]. Available: https://github.com/agra-uni-bremen/virtual-breadboard (visited on 2022-12-20)

49.

P. Pieper, V. Herdt, S. Tempel, K.A. Rudkowski, S. Ahmadi-Pour, N. Bruns, RISC-V virtual prototype (2021) [Online]. Available: https://github.com/agra-uni-bremen/riscv-vp (visited on 2022-12-20)

51.

P. Pieper, Virtual peripheral in-the-loop: protocol (2023) [Online]. Available: https://github.com/agra-uni-bremen/virtual-bus (visited on 2023-03-24)

52.

S. Ahmadi-Pour, P. Pieper, R. Drechsler, Virtual-peripheral-in-the-loop: a hardware-in-the-loop strategy to bridge the VP/RTL design-gap (2023). arXiv:2311.00442 [cs.AR]

60.

Accellera SystemC distributions (2018) [Online]. Available: https://www.accellera.org/downloads/standards/systemc (visited on 2023-04)

64.

RISCV-QEMU (2018) [Online]. Available: https://github.com/riscv/riscv-qemu (visited on 2022-04)

65.

Spike (2018) [Online]. Available: https://github.com/riscv/riscv-isa-sim (visited on 2022-04)

66.

B. Bailey, G. Martin, A. Piziali, ESL Design and Verification: A Prescription for Electronic System Level Methodology (Morgan Kaufmann/Elsevier, Burlington/Amsterdam, 2007)

67.

C. Celio, D.A. Patterson, K. Asanović, The berkeley out-of-order machine (boom): an industry-competitive, synthesizable, parameterized riscv processor, EECS Department, University of California, Berkeley, Technical Report. UCB/EECS-2015-167, 2015 [Online]. Available: http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-167.html

68.

FreeRTOS (2022) [Online]. Available: https://www.freertos.org/ (visited on 2022-04)

69.

Zephyr Project (2022) [Online]. Available: https://www.zephyrproject.org/ (visited on 2022-04)

70.

RIOT OS (2022) [Online]. Available: https://www.riot-os.org/ (visited on 2022-04)

71.

Concept Engineering GmbH, Nlview 7.3.11. https://www.concept.de,2021-04

72.

Open Hardware Foundation, Etherbone is an FPGA-core that connects ethernet to internal on-chip wishbone buses permitting any core to talk to any other across ethernet (2020) [Online]. Available: https://ohwr.org/project/etherbone-core (visited on 2023-11)

73.

V. Herdt, D. Große, H.M. Le, R. Drechsler, Extensible and configurable RISC-V based virtual prototype, in Forum on Specification and Design Languages (2018), pp. 5–16

75.

D. Große, R. Drechsler, Quality-Driven SystemC Design (Springer, Berlin, 2010)CrossRef

76.

M. Streubühr, R. Rosales, R. Hasholzner, C. Haubelt, J. Teich, ESL power and performance estimation for heterogeneous mpsocs using SystemC, in FDL (2011), pp. 1–8

77.

K. Grüttner et al., CONTREX: design of embedded mixed-criticality CONTRol systems under consideration of extra-functional properties. Microprocess. Microsyst. 51, 39–55 (2017)CrossRef

78.

G. Onnebrink, R. Leupers, G. Ascheid, S. Schürmans, Black box ESL power estimation for loosely-timed TLM models, in SAMOS (2016), pp. 366–371. https://doi.org/10.1109/SAMOS.2016.7818374

79.

V. Herdt, H.M. Le, D. Große, R. Drechsler, On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation – a case study, in FDL (2016), pp. 1–8

80.

V. Herdt, H.M. Le, D. Große, R. Drechsler, Towards early validation of firmware-based power management using virtual prototypes: a constrained random approach, in FDL (2017), pp. 1–8

81.

RV8 (2018) [Online]. Available: https://rv8.io (visited on 2022-04)

82.

DBT-RISE (2021) [Online]. Available: https://github.com/Minres/DBT-RISE-Core (visited on 2022-04)

83.

N. Binkert et al., The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1–7 (2011). ISSN: 0163-5964. https://doi.org/10.1145/2024716.2024718 [Online]. Available: http://doi.acm.org/10.1145/2024716.2024718

84.

Forvis: a formal RISC-V ISA specification (2020) [Online]. Available: https://github.com/rsnikhil/RISCV-ISA-Spec (visited on 2022-04)

85.

GRIFT - galois RISC-V ISA formal tools (2020) [Online]. Available: https://github.com/GaloisInc/grift (visited on 2022-04)

86.

RISCV sail model (2020) [Online]. Available: https://github.com/rems-project/sail-riscv (visited on 2022-04)

87.

T. Schuster, R. Meyer, R. Buchty, L. Fossati, M. Berekovic, Socrocket – a virtual platform for the European Space Agency’s SoC development, in ReCoSoC (2014), pp. 1–7

88.

GCC, the GNU compiler collection (1987) [Online]. Available: https://gcc.gnu.org/ (visited on 2023-04)

89.

S. Ahmadi-Pour, V. Herdt, R. Drechsler, The microrv32 framework: an accessible and configurable open source RISC-V cross-level platform for education and research. J. Syst. Archit. 133, 102757 (2022). ISSN: 1383-7621. https://doi.org/10.1016/j.sysarc.2022.102757 [Online]. Available: https://www.sciencedirect.com/science/article/pii/S1383762122002429

90.

S. Tempel, V. Herdt, R. Drechsler, SymEx-VP: an open source virtual prototype for OS-agnostic concolic testing of IoT firmware. J. Syst. Archit. 126, 102456 (2022). ISSN: 1383-7621. https://doi.org/10.1016/j.sysarc.2022.102456 [Online]. Available: https://www.sciencedirect.com/science/article/pii/S1383762122000480

91.

HiFive1 (2022) [Online]. Available: https://www.sifive.com/boards/hifive1 (visited on 2022-04)

92.

SiFive FE310-G000 manual (2020) [Online]. Available: https://sifive.cdn.prismic.io/sifive%2F500a69f8-af3a-4fd9-927f-10ca77077532_fe310-g000.pdf (visited on 2020-09-17)

93.

SiFive FE310-G002 datasheet v1p2 [Online]. Available: https://starfivetech.com/uploads/fe310-g002-datasheet-v1p2.pdf

94.

RISC-V ISA tests (2020) [Online]. Available: https://github.com/riscv/riscv-tests (visited on 2022-04)

95.

RISC-V torture test generator (2022) [Online]. Available: https://github.com/ucb-bar/riscv-torture (visited on 2022-04)

96.

V. Herdt, D. Große, H.M. Le, R. Drechsler, Verifying instruction set simulators using coverage-guided fuzzing, in Design, Automation and Test in Europe (2019)

97.

V. Herdt, H.M. Le, D. Große, R. Drechsler, Verifying SystemC using intermediate verification language and stateful symbolic simulation, in TCAD (2018). ISSN: 0278-0070. https://doi.org/10.1109/TCAD.2018.2846638

98.

A. Cimatti, I. Narasamdya, M. Roveri, Software model checking SystemC. TCAD 32(5), 774–787 (2013)

99.

M.Y. Vardi, Formal techniques for SystemC verification, in DAC (2007), pp. 188–192

100.

M.F. Oliveira et al., The system verification methodology for advanced tlm verification, in Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, ser. CODES+ISSS ’12, Tampere (Association for Computing Machinery, New York, 2012), pp. 313–322. ISBN: 9781450314268 [Online]. Available: https://doi.org/10.1145/2380445.2380497

101.

J. Yuan, C. Pixley, A. Aziz, Constraint-based Verification (Springer, Berlin, 2006)

102.

X. Guo, R.D. Mullins, Accelerate cycle-level full-system simulation of multi-core RISC-V systems with binary translation. CoRR vol. abs/2005.11357 (2020) [Online]. Available: https://arxiv.org/abs/2005.11357

103.

X. Guo, R.D. Mullins, Fast TLB simulation for RISC-V systems. ArXiv vol. abs/1905.06825, 2019

104.

GEM5 (2021) [Online]. Available: https://gem5.googlesource.com/public/gem5 (visited on 2022-04)

105.

ETISS (extendable translating instruction set simulator) (2022) [Online]. Available: https://github.com/tum-ei-eda/etiss (visited on 2022-04)

106.

D. Mueller-Gritschneder, M. Dittrich, M. Greim, K. Devarajegowda, W. Ecker, U. Schlichtmann, The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping, in 2017 International Symposium on Rapid System Prototyping (RSP) (2017), pp. 79–84

107.

RISC-V-TLM (2022) [Online]. Available: https://github.com/mariusmm/RISC-V-TLM (visited on 2022-04)

108.

HIFIVE1-VP (2022) [Online]. Available: https://git.minres.com/VP/HIFIVE1-VP (visited on 2022-04)

109.

Synopsis virtualizer (2021) [Online]. Available: https://www.synopsys.com/verification/virtual-prototyping/virtualizer.html (visited on 2022-04)

110.

SimAvr RISC-V ISA simulator (2020) [Online]. Available: https://github.com/buserror/simavr (visited on 2022-04)

111.

PICsimLab - programmable IC simulator laboratory (2020) [Online]. Available: https://github.com/lcgamboa/picsimlab (visited on 2022-04)

112.

Data-sheet of the SH1106 OLED display driver (2019) [Online]. Available: https://www.velleman.eu/downloads/29/infosheets/sh1106_datasheet.pdf (visited on 2023-04)

113.

L. Christensen, Chip Industry’s Technical Paper Roundup: Oct 18 (2022) [Online]. Available: https://semiengineering.com/semiconductor-industrys-technical-paper-roundup-oct-18 (visited on 2022-12-20)

114.

M. Holzer, B. Knerr, P. Belanovic, M. Rupp, G. Sauzon, Faster complex SoC design by virtual prototyping, in Int’l Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA) (2004), pp. 305–309

115.

R.M. Stallman, R. Pesch, S. Shebs et al., Debugging with GDB: the GNU source-level debugger, 10th. GNU (2020) [Online]. Available: https://sourceware.org/gdb/current/onlinedocs/gdb.pdf

116.

R. Willenberg, P. Chow, Simulation-based HW/SW co-debugging for field-programmable systems-on-chip, in Int’l Conference on Field Programmable Logic and Applications (FPL) (IEEE, Piscataway, 2013), pp. 1–8

117.

K. Lee, A. Su, L.-F. Chen, J.-W. Jhou, J. Kuo, M. Liu, A software/hardware co-debug platform for multi-core systems, in 2011 9th IEEE International Conference on ASIC (2011), pp. 259–262. https://doi.org/10.1109/ASICON.2011.6157171.

118.

F. Rogin, C. Genz, R. Drechsler, S. Rülke, An integrated SystemC debugging environment, in Embedded Systems Specification and Design Languages, ser. Lecture Notes in Electrical Engineering, vol. 10 (Springer, Berlin, 2008), pp. 59–71

119.

D. Große, R. Drechsler, L. Linhard, G. Angst, Efficient automatic visualization of SystemC designs, in FDL, ECSI (2003), pp. 646–658

120.

W. Chen, S. Ray, J. Bhadra, M. Abadir, L.-C. Wang, Challenges and trends in modern SoC design verification. IEEE Desig. Test 34(5), 7–22 (2017). https://doi.org/10.1109/mdat.2017.2735383CrossRef

121.

A. Adamov, K. Mostovaya, I. Syzonenko, A. Melnik, Electronic system level models for functional verification of system-on-chip, in 2007 9th International Conference – The Experience of Designing and Applications of CAD Systems in Microelectronics (IEEE, Piscataway, 2007). https://doi.org/10.1109/cadsm.2007.4297576

122.

S. Rigo, R. Azevedo, L. Santos (eds.), Electronic System Level Design (Springer Netherlands, Dordrecht, 2011). https://doi.org/10.1007/978-1-4020-9940-3

123.

S. Rigo, B. Albertini, R. Azevedo, Transaction level modeling, in Electronic System Level Design (Springer Netherlands, Dordrecht, 2011), pp. 25–36. https://doi.org/10.1007/978-1-4020-9940-3_3CrossRef

124.

L. Santos, S. Rigo, R. Azevedo, G. Araujo, Electronic system level design, in Electronic System Level Design (Springer Netherlands, Dordrecht, 2011), pp. 3–10. https://doi.org/10.1007/978-1-4020-9940-3_1CrossRef

125.

ISTQB, Istqb glossary, https://glossary.istqb.org/en_US/term/hardware-in-the-loop-2

126.

F. Mihalic, M. Truntic, A. Hren, Hardware-in-the-loop simulations: a historical overview of engineering challenges. Electronics 11(15) (2022). ISSN: 2079-9292. https://doi.org/10.3390/electronics11152462 [Online]. Available: https://www.mdpi.com/2079-9292/11/15/2462

127.

P. Nissimagoudar, V. Mane, G. H M, N.C. Iyer, Hardware-in-the loop (hil) simulation technique for an automotive electronics course. Procedia Comput. Sci. 172, 1047–1052 (2020). 9th World Engineering Education Forum (WEEF 2019) Proceedings : Disruptive Engineering Education for Sustainable Development. ISSN: 1877-0509. https://doi.org/10.1016/j.procs.2020.05.153 [Online]. Available: https://www.sciencedirect.com/science/article/pii/S1877050920314836

128.

C. Köhler, Enhancing Embedded Systems Simulation (Vieweg+Teubner, Berlin, 2011). https://doi.org/10.1007/978-3-8348-9916-3CrossRef

129.

A. Wu, J.-F. Mao, X. Zhang, An ADRC-based hardware-in-the-loop system for maximum power point tracking of a wind power generation system. IEEE Access 8, 226119–226130 (2020). https://doi.org/10.1109/ACCESS.2020.3045015CrossRef

130.

Z. Jiang, R. Leonard, R. Dougal, H. Figueroa, A. Monti, Processor-in-the-loop simulation, real-time hardware-in-the-loop testing, and hardware validation of a digitally-controlled, fuel-cell powered battery-charging station, in 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No. 04CH37551) (IEEE, Piscataway, 2004). https://doi.org/10.1109/pesc.2004.1355471

131.

N. Patrascoiu, A.M. Tomus, E. Angela, S. Vali, Creating hardware-in-the-loop system using virtual instrumentation, in 2011 12th International Carpathian Control Conference (ICCC) (2011), pp. 286–291. https://doi.org/10.1109/CarpathianCC.2011.5945865

132.

V. Reyes, Virtual hardware “in-the-loop”: earlier testing for automative applications, https://www.synopsys.com/cgi-bin/proto/pdfdla/docsdl/virtual_hardware_wp.pdf (2013)

133.

R. Isermann, J. Schaffnit, S. Sinsel, Hardware-in-the-loop simulation for the design and testing of engine-control systems. Control Eng. Pract. 7(5), 643–653 (1999). ISSN: 0967-0661. https://doi.org/10.1016/S0967-0661(98)00205-6CrossRef

134.

H. Szolc, T. Kryjak, Hardware-in-the-loop simulation of a UAV autonomous landing algorithm implemented in SoC FPGA, in 2022 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA) (IEEE, Piscataway, 2022). https://doi.org/10.23919/spa53010.2022.9927847

135.

M.D. Signore, V. Krovi, F. Mendel, Virtual prototyping and hardware-in-the-loop testing for musculoskeletal system analysis, in IEEE International Conference Mechatronics and Automation, 2005 (IEEE, Piscataway, 2005). https://doi.org/10.1109/icma.2005.1626579

136.

J. Reitz, A. Gugenheimer, J. Rosmann, Virtual hardware in the loop: hybrid simulation of dynamic systems with a virtualization platform, in 2020 Winter Simulation Conference (WSC) (IEEE, Piscataway, 2020). https://doi.org/10.1109/wsc48552.2020.9383963

137.

M. Lukasiewycz, S. Shreejith, S.A. Fahmy, System simulation and optimization using reconfigurable hardware, in 2014 International Symposium on Integrated Circuits (ISIC) (IEEE, Piscataway, 2014). https://doi.org/10.1109/isicir.2014.7029545

Title: Hardware and Environment Modeling
Authors: Pascal Pieper
Rolf Drechsler
Publisher: Springer Nature Switzerland
Book: Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes
Print ISBN: 978-3-031-51691-7

Electronic ISBN: 978-3-031-51692-4

Copyright Year: 2024
DOI: https://doi.org/10.1007/978-3-031-51692-4_3