High Reliability Soft Error Hardened Latch Design for Nanoscale CMOS Technology using PVT Variation

In this paper, a soft error hardened circuit with the aim ofavoiding and detecting-correctingthe soft error strikesat the same timing phase is proposed for high-speed memory applications. The proposed design is completely immune to multiple soft errors occurring in any of the nodes. The avoidance part and detection-correction part are the two major parts that tolerate multiple particle strikes. The proposed design can detect and correct a single particle strike at single node and at multiple nodes.A set of simulations are made in CMOS technology to validate the proposed circuit in terms of delay, power, and area overheads which are the main requirements of VLSI design. Compared with other techniques it is shown that the proposed circuit achieves 1.124 μm power consumption, and142.68ps delay overheads. The work also investigates about Monte Carlo simulations along with the impact of process, voltage and temperature (PVT) variations and shows that the proposed circuit is highly reliable and less sensitive to soft errors compared with other existing soft error latches.