Implementation and Performance Analysis of True Random Number Generator on FPGA Environment by Using Non-periodic Chaotic Signals Obtained from Chaotic Maps

In this study, FPGA implementation of a hybrid random number generator (HRNG) based on digital design techniques is given. The ring oscillators (ROs) are used as the noise source of HRNG, and true randomness is obtained by sampling jitter signals forming on the oscillators. The statistical quality and reliability of random number generators that used jitter as source of true randomness alone are often cryptographically insufficient. For this reason, one-dimensional discrete-time chaotic maps such as quadratic map, logistic map and Bernoulli shift map are benefited in order for HRNG to meet these cryptographic requirements. In contrast to many studies in the literature, non-periodic signals derived from chaotic systems of a powerful source of entropy are used instead of periodic signals for the sampling of jitter signals in the system. Depending on the usage of chaotic systems, output bit rate and reliability of high generator model that does not need post-processing techniques and is easily applicable to digital devices are obtained. The hybrid system is tested in total six different scenarios for two separate ring oscillator (RO) architectures of 25 and 114 pieces consisting of three different chaotic maps and equal-length inverters. The statistical qualifications of the random numbers obtained from HRNG for each scenario are verified by NIST 800-22 tests. Also, for each scenario, the design parameters of the generator are examined and the hardware performances and non-periodicity analyses of the chaotic maps are performed. Based on the obtained results, it is demonstrated that the HRNG based on non-periodic sampling can be used for cryptographic purposes.