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2016 | OriginalPaper | Chapter

Implementation of Reversible Arithmetic and Logical Unit and Its BILBO Testing

Authors : Sk. Bajidbi, M. S. S. Rukmini, Y. Ratna Babu

Published in: Microelectronics, Electromagnetics and Telecommunications

Publisher: Springer India

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Abstract

Reversible logic is gaining more importance day by day, because of its feature of low power dissipation which is the basic need in designing nano electronic devices, bioinformatics, low power CMOS designs and quantum computing. Reversible logic is one which realizes n-input n-output functions that map each possible input vector to a unique output vector. It is a promising computer design paradigm for constructing arithmetic and logic units which are the basic building blocks of computer that do not dissipate heat. After designing a system, it is also equal important to test it. In this paper reversible ALU (Arithmetic and Logical Unit) performing four operations (Addition, Multiplication, Subtraction and Bit wise- AND) is implemented and the simulated results like power consumed, delay and area obtained are compared with that of conventional ALU. Testing is also done on proposed reversible ALU by using BILBO (Built—in Logic Block Observer) blocks, which was the first BIST (Built-in Self Test) architecture to be proposed and undergo wide spread use. The proposed reversible ALU is implemented and simulated using Verilog HDL in Xilinx 13.4 version.

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Literature
1.
go back to reference H. Thapliyal, N. Ranganathan, S. Kotiyal, Design of testable reversible sequential circuits. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 21(7) (2013) H. Thapliyal, N. Ranganathan, S. Kotiyal, Design of testable reversible sequential circuits. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 21(7) (2013)
2.
go back to reference B. Raghu Kanth, B. Murali Krishna, M. Sridhar, V.G. Santhi Swaroop, A distinguish between reversible and conventional logic gates. Int. J. Eng. Res. Appl. (IJERA) 2(2), 148–151 (2012). ISSN: 2248–9622 B. Raghu Kanth, B. Murali Krishna, M. Sridhar, V.G. Santhi Swaroop, A distinguish between reversible and conventional logic gates. Int. J. Eng. Res. Appl. (IJERA) 2(2), 148–151 (2012). ISSN: 2248–9622
3.
go back to reference H.R. Bhagyalakshmi, M.K. Venkatesha, An improved design of a multiplier using reversible logic gates. Int. J. Eng. Sci. Technol. 2(8), 3838–3845 (2010) H.R. Bhagyalakshmi, M.K. Venkatesha, An improved design of a multiplier using reversible logic gates. Int. J. Eng. Sci. Technol. 2(8), 3838–3845 (2010)
4.
go back to reference H. Thapliyal, N. Ranganathan, Cirucit for reversible quantum multiplier on binary tree optimizing ancilla and garbage bits. In: Proceedings of the 27th International Conference on VLSI Design, Mumbai, India, Jan 2014 H. Thapliyal, N. Ranganathan, Cirucit for reversible quantum multiplier on binary tree optimizing ancilla and garbage bits. In: Proceedings of the 27th International Conference on VLSI Design, Mumbai, India, Jan 2014
5.
go back to reference A. Jamal, J.P. Prasad, Design of low power counters using reversible logic. Int. J. Innov. Res. Sci. Eng. Technol. 3(5) (2014). An ISO:3297:2007 Certified Organization A. Jamal, J.P. Prasad, Design of low power counters using reversible logic. Int. J. Innov. Res. Sci. Eng. Technol. 3(5) (2014). An ISO:3297:2007 Certified Organization
6.
go back to reference J.P. Hayes, I. Polian, B. Becker, Testing For missing gate faults in reversible circuits. In Proceedings of 13th Asian Test Symposium, 2004, pp. 100–105 J.P. Hayes, I. Polian, B. Becker, Testing For missing gate faults in reversible circuits. In Proceedings of 13th Asian Test Symposium, 2004, pp. 100–105
7.
go back to reference M. Morrison, N. Ranganathan, Design of a reversible ALU based on novel programmable reversible logic gate structures. To Appear In The IEEE International Symposium on VLSI (2011) M. Morrison, N. Ranganathan, Design of a reversible ALU based on novel programmable reversible logic gate structures. To Appear In The IEEE International Symposium on VLSI (2011)
8.
go back to reference M. Suresh, A.K. Panda, M.K. Sukla, Design of arithmetic circuits using reversible logic gates and power. In International Symposium on Electronic System Design (2010) M. Suresh, A.K. Panda, M.K. Sukla, Design of arithmetic circuits using reversible logic gates and power. In International Symposium on Electronic System Design (2010)
9.
go back to reference A. Banerjee, A. Pathak, Reversible multiplier circuit. In Proceedings of 3rd International Conference on Emerging Trends in Engineering and Technology, 2010, pp. 781–786 A. Banerjee, A. Pathak, Reversible multiplier circuit. In Proceedings of 3rd International Conference on Emerging Trends in Engineering and Technology, 2010, pp. 781–786
10.
go back to reference M. Perkowski, J. Biamonte, M. Lukac, Test generation and fault localization for quantum circuits. In Proceedings of 35th IEEE International Symposium on Multiple Valued Logic, 2005, pp. 62–65 M. Perkowski, J. Biamonte, M. Lukac, Test generation and fault localization for quantum circuits. In Proceedings of 35th IEEE International Symposium on Multiple Valued Logic, 2005, pp. 62–65
11.
go back to reference B. Premananda, Y.M. Rravindhranath, Design and synthesis of 16 bit ALU using reversible logic gates. Int. J. Adv. Res. Commun. Eng. 2(10), 2278–1021 (2013). ISSN(Print):2319–5940. ISSN(Online):Business Media New York 2014 B. Premananda, Y.M. Rravindhranath, Design and synthesis of 16 bit ALU using reversible logic gates. Int. J. Adv. Res. Commun. Eng. 2(10), 2278–1021 (2013). ISSN(Print):2319–5940. ISSN(Online):Business Media New York 2014
12.
go back to reference Y. Ratna Babu, Y. Syamala, Implementation and testing of multipliers using reversible logic. Int. Conf. Adv. Recent Technol. Commun. Comput. (2011) Y. Ratna Babu, Y. Syamala, Implementation and testing of multipliers using reversible logic. Int. Conf. Adv. Recent Technol. Commun. Comput. (2011)
13.
go back to reference Y. Syamala, A.V.N. Tilak, Synthesis of multiplexer and demultiplexer circuits using reversible logic. Int. J. Recent Trends Eng. Technol. 4(3), 34–35 (2010) Y. Syamala, A.V.N. Tilak, Synthesis of multiplexer and demultiplexer circuits using reversible logic. Int. J. Recent Trends Eng. Technol. 4(3), 34–35 (2010)
14.
go back to reference B. Konemann, J. Mucha, G. Zwiehoff, Built-in logic block observation techniques. In Proceedings of IEEE Test Conference, 1979, pp. 37–41 B. Konemann, J. Mucha, G. Zwiehoff, Built-in logic block observation techniques. In Proceedings of IEEE Test Conference, 1979, pp. 37–41
15.
go back to reference I. Polian, T. Fiehn, J.P. Hayes, A family of logical fault models for reversible circuits. In Proceedings of 14th Asian Test Symposium, 2005, pp. 422–427 I. Polian, T. Fiehn, J.P. Hayes, A family of logical fault models for reversible circuits. In Proceedings of 14th Asian Test Symposium, 2005, pp. 422–427
16.
go back to reference J. Chen, D.P. Vasudevan, E. Popovici, M. Schellekensm, Reversible online bist using bidirectional Bilbo. In Proceedings of ACM International Conference on Computing Frontiers, 2010, pp. 257–266 J. Chen, D.P. Vasudevan, E. Popovici, M. Schellekensm, Reversible online bist using bidirectional Bilbo. In Proceedings of ACM International Conference on Computing Frontiers, 2010, pp. 257–266
Metadata
Title
Implementation of Reversible Arithmetic and Logical Unit and Its BILBO Testing
Authors
Sk. Bajidbi
M. S. S. Rukmini
Y. Ratna Babu
Copyright Year
2016
Publisher
Springer India
DOI
https://doi.org/10.1007/978-81-322-2728-1_57