Introduction

This book is devoted to an in-depth study of logic synthesis techniques for asynchronous control circuits. These are logic circuits that do not rely on global synchronization signals, the clocks, to dictate the interval of time at which other signals are sampled. The difficulty with their design is well known since the late 1950’s. Asynchronous circuits cannot distinguish between combinational behavior, governed by Boolean algebra, and sequential behavior, governed by Finite State Machine (FSM) algebra. This separation, together with static timing analysis to compute minimum clock cycles, is essential to modern synchronous logic design. Asynchronous circuits can still, by means of appropriate delay models, abstract away most complex electric and timing properties of transistors and wires. However, both synthesis and analysis of asynchronous circuits must consider everything as sequential, and hence are subject to the state explosion problem which plagues the sequential world.